公开(公告)号：US08089120B2

公开(公告)日：2012-01-03

申请号：US12562781

申请日：2009-09-18

申请人： Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Yoshiaki Fukuzumi

发明人： Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Yoshiaki Fukuzumi

IPC分类号： H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11578 ,  H01L27/11582

摘要： A semiconductor memory device includes: a semiconductor substrate; a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked, the stacked body being provided on the semiconductor substrate; a semiconductor layer provided inside a hole formed through the stacked body, the semiconductor layer extending in stacking direction of the conductive layers and the dielectric layers; and a charge storage layer provided between the conductive layers and the semiconductor layer. The stacked body in a memory cell array region including a plurality of memory strings is divided into a plurality of blocks by slits with an interlayer dielectric film buried therein, the memory string including as many memory cells series-connected in the stacking direction as the conductive layers, the memory cell including the conductive layer, the semiconductor layer, and the charge storage layer provided between the conductive layer and the semiconductor layer, and each of the block is surrounded by the slits formed in a closed pattern.

摘要翻译： 半导体存储器件包括：半导体衬底; 具有交替堆叠的多个导电层和多个电介质层的层叠体，所述层叠体设置在所述半导体基板上; 设置在通过所述层叠体形成的孔内的半导体层，所述半导体层沿所述导电层和所述电介质层的堆叠方向延伸; 以及设置在导电层和半导体层之间的电荷存储层。 包含多个存储器串的存储单元阵列区域中的堆叠体被埋置在其中的层间电介质膜的狭缝分成多个块，该存储串包括在堆叠方向上串联连接的存储单元作为导电 存储单元包括导电层，半导体层和设置在导电层和半导体层之间的电荷存储层，并且每个块被形成为封闭图案的狭缝包围。

公开(公告)号：US08008710B2

公开(公告)日：2011-08-30

申请号：US12501142

申请日：2009-07-10

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C5/02 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  G11C16/0483 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42348 ,  H01L29/7926

摘要： A memory string has a semiconductor layer with a joining portion that is formed to join a plurality of columnar portions extending in a vertical direction with respect to a substrate and lower ends of the plurality of columnar portions. First conductive layers are formed in a laminated fashion to surround side surfaces of the columnar portions and an electric charge storage layer, and function as control electrodes of memory cells. A second conductive layer is formed around the plurality of columnar portions via a gate insulation film, and functions as control electrodes of selection transistors. Bit lines are formed to be connected to the plurality of columnar portions, respectively, with a second direction orthogonal to a first direction taken as a longitudinal direction.

摘要翻译： 存储器串具有半导体层，其具有接合部分，该接合部分形成为连接相对于衬底在垂直方向上延伸的多个柱状部分和多个柱状部分的下端。 第一导电层以叠层的方式形成以包围柱状部分的侧表面和电荷存储层，并且用作存储单元的控制电极。 通过栅极绝缘膜在多个柱状部分周围形成第二导电层，并且用作选择晶体管的控制电极。 位线分别形成为与第一方向正交的第二方向作为纵向连接到多个柱状部分。

公开(公告)号：US20110031550A1

公开(公告)日：2011-02-10

申请号：US12727712

申请日：2010-03-19

申请人： Yosuke Komori ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Yosuke Komori ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes: a stacked structural unit including a plurality of electrode films and a plurality of inter-electrode insulating films alternately stacked in a first direction; a first selection gate electrode stacked on the stacked structural unit in the first direction; a first semiconductor pillar piercing the stacked structural unit and the first selection gate electrode in the first direction; a first memory unit provided at an intersection of each of the electrode films and the first semiconductor pillar; and a first selection gate insulating film provided between the first semiconductor pillar and the first selection gate electrode, the first selection gate electrode including a first silicide layer provided on a face of the first selection gate electrode perpendicular to the first direction.

摘要翻译： 非易失性半导体存储器件包括：堆叠结构单元，包括多个电极膜和沿第一方向交替堆叠的多个电极间绝缘膜; 第一选择栅电极，沿第一方向堆叠在层叠结构单元上; 第一半导体柱在第一方向上穿透层叠结构单元和第一选择栅电极; 设置在每个电极膜和第一半导体柱的交点处的第一存储单元; 以及设置在所述第一半导体柱和所述第一选择栅极之间的第一选择栅极绝缘膜，所述第一选择栅电极包括设置在所述第一选择栅电极的与所述第一方向垂直的面上的第一硅化物层。

公开(公告)号：US20110012188A1

公开(公告)日：2011-01-20

申请号：US12728658

申请日：2010-03-22

申请人： Masaru KITO ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Hideaki Aochi

发明人： Masaru KITO ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Hideaki Aochi

IPC分类号： H01L27/105

CPC分类号： H01L27/11578 ,  H01L27/11582

摘要： A semiconductor memory device includes: a stacked body formed of a plurality of inter-layer insulating films and a plurality of electrode films alternately stacked and having a through-hole formed in the stacking direction; an electrode-side insulating film of a film thickness of 4 nm or more provided on an inner surface of the through-hole; a charge storage film provided on the electrode-side insulating film; a semiconductor-side insulating film of a film thickness of 4 nm or more provided on the charge storage film; and a semiconductor pillar buried in the through-hole.

摘要翻译： 半导体存储器件包括：由多个层间绝缘膜和交替层叠并具有沿堆叠方向形成的通孔的多个电极膜形成的层叠体; 设置在通孔的内表面上的膜厚度为4nm以上的电极侧绝缘膜; 设置在电极侧绝缘膜上的电荷存储膜; 设置在电荷存储膜上的膜厚度为4nm以上的半导体侧绝缘膜; 以及埋在通孔中的半导体柱。

公开(公告)号：US20100224928A1

公开(公告)日：2010-09-09

申请号：US12714905

申请日：2010-03-01

申请人： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa

发明人： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa

IPC分类号： H01L29/792 ,  H01L21/8239

CPC分类号： H01L27/11578 ,  H01L21/28282 ,  H01L27/11582

摘要： A method for manufacturing a nonvolatile semiconductor memory device, the device including a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction and a semiconductor pillar piercing the stacked structural unit in the first direction, the method includes: forming a stacked unit including a core material film alternately stacked with a sacrificial film on a major surface of a substrate perpendicular to the first direction; making a trench in the stacked unit, the trench extending in the first direction and a second direction in a plane perpendicular to the first direction; filling a filling material into the trench; removing the sacrificial film to form a hollow structural unit, the hollow structural unit including a post unit supporting the core material film on the substrate, the post unit being made of the filling material; and forming the stacked structural unit by stacking one of the insulating films and one of the electrode films on a surface of the core material film exposed by removing the sacrificial film.

摘要翻译： 一种用于制造非易失性半导体存储器件的方法，该器件包括层叠结构单元，该堆叠结构单元包括在第一方向上交替堆叠多个电极膜的多个绝缘膜，以及沿第一方向穿透层叠结构单元的半导体柱， 方法包括：在垂直于第一方向的基板的主表面上形成包括交替堆叠有牺牲膜的芯材膜的堆叠单元; 在所述堆叠单元中形成沟槽，所述沟槽在垂直于所述第一方向的平面中沿所述第一方向延伸并且沿第二方向延伸; 将填充材料填充到沟槽中; 去除所述牺牲膜以形成中空结构单元，所述中空结构单元包括支撑所述芯材膜的柱单元，所述柱单元由所述填充材料制成; 以及通过将绝缘膜和其中一个电极膜层叠在通过去除牺牲膜而暴露的芯材膜的表面上来形成层叠结构单元。

公开(公告)号：US08728919B2

公开(公告)日：2014-05-20

申请号：US13723601

申请日：2012-12-21

申请人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Megumi Ishiduki ,  Yosuke Komori ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi

发明人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Megumi Ishiduki ,  Yosuke Komori ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi

IPC分类号： H01L21/20

CPC分类号： H01L29/7926 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7881

摘要： A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.

摘要翻译： 非挥发性半导体存储装置包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元。 每个存储器串包括：第一半导体层，包括相对于衬底在垂直方向上延伸的柱状部分; 多个第一导电层，经由绝缘层形成为围绕柱状部分的侧表面，并以垂直方向上的一定间距形成，第一导电层用作存储器单元的浮动栅极; 以及形成为经由绝缘层包围第一导电层并且用作存储单元的控制电极的多个第二导电层。 每个第一导电层在垂直方向上具有比每个第二导电层的垂直方向上的长度短的长度。

公开(公告)号：US08436414B2

公开(公告)日：2013-05-07

申请号：US12706127

申请日：2010-02-16

申请人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Junya Matsunami ,  Ryouhei Kirisawa

发明人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Junya Matsunami ,  Ryouhei Kirisawa

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 设置在所述半导体基板上的层叠体，具有交替堆叠的电极膜和绝缘膜的层叠体， 第一和第二半导体柱; 以及第一和第二电荷存储层。 第一半导体柱和第二半导体柱设置在层叠体的层叠方向上贯穿层叠体的贯通孔内。 当沿垂直于堆叠方向的方向切割时，通孔具有扁圆形的横截面。 第一和第二半导体柱在第一扁圆的长轴方向上彼此面对。 第一和第二半导体柱沿层叠方向延伸。 第一和第二电荷存储层分别设置在电极膜和第一和第二半导体柱之间。

公开(公告)号：US08247863B2

公开(公告)日：2012-08-21

申请号：US12708161

申请日：2010-02-18

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A memory string comprises: a pair of columnar portions; a first insulating layer surrounding a side surface of the columnar portions; a charge storage layer surrounding a side surface of the first insulating layer; a second insulating layer surrounding a side surface of the charge storage layer; and a first conductive layer surrounding a side surface of the second insulating layer. A select transistor comprises: a second semiconductor layer extending from an upper surface of the columnar portions; a third insulating layer surrounding a side surface of the second semiconductor layer; a fourth insulating layer surrounding a side surface of the third insulating layer; and a second conductive layer surrounding a side surface of the fourth insulating layer. The first semiconductor layer is formed continuously in an integrated manner with the second semiconductor layer. The first insulating layer is formed continuously in an integrated manner with the third insulating layer.

摘要翻译： 存储器串包括：一对柱状部分; 围绕所述柱状部分的侧表面的第一绝缘层; 围绕所述第一绝缘层的侧表面的电荷存储层; 围绕电荷存储层的侧表面的第二绝缘层; 以及围绕所述第二绝缘层的侧表面的第一导电层。 选择晶体管包括：从柱状部分的上表面延伸的第二半导体层; 围绕所述第二半导体层的侧表面的第三绝缘层; 围绕所述第三绝缘层的侧表面的第四绝缘层; 以及围绕所述第四绝缘层的侧表面的第二导电层。 第一半导体层以与第二半导体层一体化的方式连续地形成。 第一绝缘层与第三绝缘层一体地形成。

公开(公告)号：US08189371B2

公开(公告)日：2012-05-29

申请号：US12851002

申请日：2010-08-05

申请人： Ryota Katsumata ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Ryota Katsumata ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： G11C11/14

CPC分类号： G11C16/0483 ,  G11C16/06 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a stacked body, a through-hole, a semiconductor pillar, and a charge storage film. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in the through-hole. The charge storage film is provided between the electrode films and the semiconductor pillar. Memory cells are formed at each intersection between the electrode films and the semiconductor pillar. The control circuit writs a first value to at least some of the memory cells, performs an erasing operation of the first value from the memory cell written with the first value, reads data stored in the memory cell having undergone the erasing operation, and sets the memory cell to be unusable in a case that the first value is read from the memory cell.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制电路。 存储单元阵列包括层叠体，通孔，半导体柱和电荷存储膜。 层叠体包括交替层叠有多个电极膜的多个绝缘膜。 通孔形成在堆叠体中以沿堆叠方向对齐。 半导体柱埋在通孔中。 电荷存储膜设置在电极膜和半导体柱之间。 在电极膜和半导体柱之间的每个交叉处形成存储单元。 控制电路将第一值写入至少部分存储单元，从写入第一值的存储单元执行第一值的擦除操作，读取存储在经过擦除操作的存储单元中的数据，并将 在从存储器单元读取第一值的情况下，存储器单元不可用。

公开(公告)号：US08188530B2

公开(公告)日：2012-05-29

申请号：US12728727

申请日：2010-03-22

申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L21/8239 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L27/11578 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conductive layer.

摘要翻译： 一种设置有单元阵列部分和外围电路部分的半导体存储器件，该器件包括：背栅电极; 设置在所述背栅电极上的层叠体; 沿层叠方向延伸的多个半导体柱; 连接构件，每个连接构件将半导体柱之一连接到另一个半导体柱; 向所述背栅电极施加电位的背栅极电极接触; 设置在所述外围电路部中的栅电极; 以及向所述栅电极，所述背栅电极和所述栅电极施加电位的栅电极接触部，分别包括：下半导体层; 设置在下半导体层上的导电层; 以及设置在所述导电层上的上半导体层，所述连接构件设置在所述上​​半导体层中或所述上半导体层上，所述背栅电极接触和所述栅电极接触与所述导电层接触。