公开(公告)号：US07554309B2

公开(公告)日：2009-06-30

申请号：US11132750

申请日：2005-05-18

申请人： John H. Carpenter, Jr. ,  Brett J. Thompsen ,  Benjamin L. Amey ,  Zhihong You ,  Joseph A. Devore

发明人： John H. Carpenter, Jr. ,  Brett J. Thompsen ,  Benjamin L. Amey ,  Zhihong You ,  Joseph A. Devore

IPC分类号： G05F1/40

CPC分类号： G05F1/618

摘要： Systems, methods and circuits for regulator minimum load control. In one particular case, a system is provided that includes a load control circuit and a switched load. The load control circuit includes a reference current, and a sense current representative of a load current. In addition, the load control circuit includes a comparator circuit that drives a control signal in response to a comparison between the reference current and the sense current. The switched load is electrically coupled to a load voltage signal to provide loading to the load voltage signal. The switched load is operable to switch between a first loading factor and a second loading factor in response to the control signal.

摘要翻译： 用于调节器最小负载控制的系统，方法和电路。 在一个特定情况下，提供了包括负载控制电路和开关负载的系统。 负载控制电路包括参考电流和代表负载电流的感测电流。 此外，负载控制电路包括响应于参考电流和感测电流之间的比较来驱动控制信号的比较器电路。 开关负载电耦合到负载电压信号以向负载电压信号提供负载。 切换负载可操作以响应于控制信号而在第一负载系数和第二负载系数之间切换。

公开(公告)号：US5793245A

公开(公告)日：1998-08-11

申请号：US731629

申请日：1996-10-15

申请人： Andrew Marshall ,  Joseph A. Devore ,  Raymond T. Summerlin

发明人： Andrew Marshall ,  Joseph A. Devore ,  Raymond T. Summerlin

IPC分类号： H03K17/16

CPC分类号： H03K17/162

摘要： A switch mode regulator circuit is provided to facilitate the conversion from one voltage level to another in a substantially power lossless manner. The circuit is particularly advantageous in instances where the power supply can be operable in a discontinuous mode, as inductor-capacitor oscillatory transients ("ringing"), along with its associated voltage spikes at the associated output transistor source, can be avoided. Such transients and their associated voltages are avoided by clamping the gate-source voltage on the circuit's output NMOS transistor over the entire positive operation voltage range.

摘要翻译： 提供了一种开关模式调节器电路，以便以基本上功率无损的方式从一个电压电平转换到另一个电压电平。 该电路在电源可以以不连续模式工作的情况下是特别有利的，因为可以避免电感器 - 电容器振荡瞬变（“振铃”）连同其相关联的输出晶体管源处的相关电压尖峰。 通过在整个正工作电压范围内将栅极 - 源极电压钳位在电路的输出NMOS晶体管上来避免这种瞬变及其相关电压。

公开(公告)号：US06600205B2

公开(公告)日：2003-07-29

申请号：US10062215

申请日：2002-02-01

申请人： John H. Carpenter, Jr. ,  Joseph A. Devore ,  Toru Tanaka

发明人： John H. Carpenter, Jr. ,  Joseph A. Devore ,  Toru Tanaka

IPC分类号： H01L2900

CPC分类号： H01L21/823493 ,  H01L27/088 ,  H01L29/1087

摘要： A high-breakdown voltage transistor (30; 30′) is disclosed. The transistor (30; 30′) is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed into an epitaxial layer (43) of the substrate (42). The deep well (50) is also used, by itself, for the formation of high-voltage transistors, while the shallower well (44) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or “back-gate-to-substrate”) junction breakdown.

摘要翻译： 公开了一种高耐压晶体管（30; 30'）。 晶体管（30; 30'）形成为阱布置，其中浅的，重掺杂的阱（44）至少部分地设置在更深，更轻掺杂的阱（50）内，两者都形成为外延层 （42）的（43）。 深阱（50）本身也用于形成高压晶体管，而较浅的阱（44）本身用于低电压，高性能的晶体管。 这种结构允许在高偏压应用中使用高性能和精确匹配的晶体管，而不用担心体对衬底（或“背栅极到衬底”）结击穿。

公开(公告)号：US06469884B1

公开(公告)日：2002-10-22

申请号：US09472710

申请日：1999-12-24

申请人： John H. Carpenter, Jr. ,  Joseph A. Devore ,  Reed Adams ,  Ross Teggatz

发明人： John H. Carpenter, Jr. ,  Joseph A. Devore ,  Reed Adams ,  Ross Teggatz

IPC分类号： H02H322

CPC分类号： G11C17/18

摘要： An integrated circuit (10) having at least one programmable fuse (F1) and ESD circuitry (MN3, MN1) preventing the fuse (F1) from being unintentionally blown when a voltage transient exists on a main voltage potential (Vmain). The ESD circuitry preferably comprises of MOSFET switches which are coupled to turn on quicker than a main fuse programming switch (MNmain) due to the voltage transient, thereby insuring that the main switch remains off during the voltage transient to prevent the unintentional blowing of the fuse F1. The circuit is well suited for programmable logic device (PLDs), allowing for read voltages as low as 6 volts, and allowing for programming voltages as high as 40 volts.

摘要翻译： 具有至少一个可编程熔丝（F1）和ESD电路（MN3，MN1）的集成电路（10）防止当在主电压电位（Vmain）上存在电压瞬变时熔丝（F1）被无意地烧断。 ESD电路优选地包括MOSFET开关，其由于电压瞬变而被耦合以比主熔丝编程开关（MNmain）更快地接通，从而确保主开关在电压瞬变期间保持关断以防止熔丝的无意的吹动 F1。 该电路非常适用于可编程逻辑器件（PLD），允许低至6伏的读取电压，并允许高达40伏的编程电压。

公开(公告)号：US06268755B1

公开(公告)日：2001-07-31

申请号：US08963836

申请日：1997-11-04

申请人： R. Travis Summerlin ,  Joseph A. Devore ,  William E. Grose

发明人： R. Travis Summerlin ,  Joseph A. Devore ,  William E. Grose

IPC分类号： H03K190185

CPC分类号： H03K19/018585 ,  H03K19/00361

摘要： A voltage level shifting circuit (60) and method for accomplishing a voltage level change includes a voltage level shifting circuit (65) to change an input voltage to a shifted voltage level. A second stage (67) is connected between a voltage source at the shifted voltage level (68) and the reference potential. The second stage (67) includes active devices (66,82) that are controlled by the voltage level shifting circuit (65). The second stage (67) also includes slope resistors (86,88) connected in series between the active devices (66,82) of the second stage (67).

摘要翻译： 电压电平移动电路（60）和用于实现电压电平变化的方法包括将输入电压改变到移位的电压电平的电压电平移位电路（65）。 第二级（67）连接在变换的电压电平（68）的电压源和参考电位之间。 第二级（67）包括由电压电平移位电路（65）控制的有源器件（66,82）。 第二级（67）还包括串联连接在第二级（67）的有源器件（66,82）之间的斜率电阻器（86,88）。