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公开(公告)号：US20110320881A1
公开(公告)日：2011-12-29
申请号：US12822508
申请日：2010-06-24
申请人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
发明人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
IPC分类号： G06F11/34
CPC分类号： G06F11/10 , G06F11/2005 , H04L1/0061 , H04L2001/0096
摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
摘要翻译： 隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法检测到错误状况，并且确定错误状况被隔离为单个 传输链路。 在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。 如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。
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公开(公告)号：US08082474B2
公开(公告)日：2011-12-20
申请号：US12165799
申请日：2008-07-01
CPC分类号： G06F11/167 , G06F11/073 , G06F11/076 , G06F11/1004 , G06F11/2007 , G11C5/04 , G11C29/02 , G11C29/022
摘要： Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition, shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare Shadow counters are used to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译： 阴影选择逻辑用于选择驱动程序位位置作为阴影驱动程序值，线路驱动程序可以在总线的单独链路段上传输所选驱动程序位位置和阴影驱动程序值的数据。 此外，阴影比较逻辑用于将所选接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较阴影计数器用于计算相对于总线错误的误比率 率一段时间。 响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。
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公开(公告)号：US07729153B2
公开(公告)日：2010-06-01
申请号：US12060998
申请日：2008-04-02
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.
摘要翻译： 双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将 打包内存界面。 该卡片包括至少276个配置在其上的针脚。
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24.发明申请公开(公告)号：US20100005281A1
公开(公告)日：2010-01-07
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G06F9/24
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译： 用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。 存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。 该接口可在SBC模式和高速模式下工作。 存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。 此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。
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25.发明授权276-Pin buffered memory module with enhanced fault tolerance and a performance-optimized pin assignment 失效276引脚缓冲存储器模块，具有增强的容错能力和性能优化的引脚分配公开(公告)号：US07529112B2
公开(公告)日：2009-05-05
申请号：US11695679
申请日：2007-04-03
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon including a plurality of high-speed bus interface pills arranged on said card for communicating with a plurality of high-speed busses. The high-speed bus interface pins associated with a single high-speed bus are located on one side of the card with respect to a midpoint of the length of the card, thus the pin assignments are defined such that the performance of the DIMM in a system is optimized for high frequency operation.
摘要翻译： 双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将 打包内存界面。 该卡包括至少276个引脚，其构造为包括布置在所述卡上的多个高速总线接口卡，用于与多个高速总线通信。 与单个高速总线相关联的高速总线接口引脚相对于卡的长度的中点位于卡的一侧，因此引脚分配被定义为使得DIMM的性能在 系统针对高频操作进行了优化。
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公开(公告)号：US07403409B2
公开(公告)日：2008-07-22
申请号：US11735640
申请日：2007-04-16
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.
摘要翻译： 双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将 打包内存界面。 该卡片包括至少276个配置在其上的针脚。
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公开(公告)号：US20100005335A1
公开(公告)日：2010-01-07
申请号：US12165858
申请日：2008-07-01
CPC分类号： G06F11/2007
摘要： A processing device, system, method, and design structure for providing a microprocessor interface with dynamic segment sparing and repair. The processing device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译： 一种处理设备，系统，方法和设计结构，用于提供具有动态段保存和修复的微处理器接口。 处理装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。 该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段 。
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28.发明授权System, method and storage medium for deriving clocks in a memory system 失效用于在存储器系统中导出时钟的系统，方法和存储介质公开(公告)号：US07478259B2
公开(公告)日：2009-01-13
申请号：US11263344
申请日：2005-10-31
IPC分类号： G06F1/00
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A system, method and storage medium for deriving clocks in a memory system. The method includes receiving a reference oscillator clock at a hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译： 一种用于在存储器系统中导出时钟的系统，方法和存储介质。 该方法包括在集线器装置处接收参考振荡器时钟。 集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。 以基准时钟频率工作的基本时钟从参考振荡器时钟导出。 通过将基本时钟乘以存储器乘法器导出存储器接口时钟。 控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。 存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。
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29.发明授权Apparatus and method for recalibrating a source-synchronous pipelined self-timed bus interface 有权用于重新校准源同步流水线自定时总线接口的装置和方法公开(公告)号：US06922789B2
公开(公告)日：2005-07-26
申请号：US09960023
申请日：2001-09-21
CPC分类号： H04L7/10 , G06F11/00 , H04L7/0008
摘要： An SMP computer system has an apparatus and method for recalibrating a self-timed, source-synchronous, pipelined interface while the computer system is running. The apparatus allows for quiescing the interface (ie. idling the processors to allow for no data transfers), raising fences (blocking interfaces), allowing for a quick clock centering recalibration step, and then unfencing and unquiescing to allow for the use of the interface again. The recalibration allows for compensating for drift over time on the interface to compensate for temperature, voltage, cycle time, and end-of-life degradation without bringing down and restarting the system.
摘要翻译： SMP计算机系统具有在计算机系统运行时重新校准自定时，源同步，流水线接口的装置和方法。 该设备允许停顿接口（即空闲处理器以允许不进行数据传输），提高栅栏（阻塞接口），允许快速的时钟定心重新校准步骤，然后解码和解码以允许使用接口 再次。 重新校准可以补偿接口上随时间的漂移，以补偿温度，电压，循环时间和使用寿命结束后的降低，而不会导致系统重新启动和重新启动。
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30.发明授权Circuit and method for reading data transfers that are sent with a source synchronous clock signal 失效用于读取与源同步时钟信号一起发送的数据传输的电路和方法公开(公告)号：US06807125B2
公开(公告)日：2004-10-19
申请号：US10225871
申请日：2002-08-22
IPC分类号： G11C1100
CPC分类号： G11C7/106 , G11C7/1045 , G11C7/1051 , G11C7/1066
摘要： A circuit and method for reading data transfers that are sent with a source synchronous clock signal. The circuit has a data input for receiving data signals carrying data being transferred, a clock input for receiving synchronous clock signals, and a delay circuit connected to the clock input for generating a delayed clock signal which is delayed from said synchronous clock signal a predetermined time period. The circuit also includes a pipeline connected to the data input for sampling the data on the data input in response to said delayed clock signal thereby stretching the sampling of incoming data.
摘要翻译： 用于读取与源同步时钟信号一起发送的数据传输的电路和方法。 该电路具有数据输入端，用于接收承载传送数据的数据信号，用于接收同步时钟信号的时钟输入端和连接到时钟输入端的延迟电路，用于产生从所述同步时钟信号延迟预定时间的延迟时钟信号 期。 电路还包括连接到数据输入端的流水线，用于响应于所述延迟的时钟信号对数据输入上的数据进行采样，从而延伸输入数据的采样。
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