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    Split-gate memory cells and fabrication methods thereof
    21.
    发明申请
    Split-gate memory cells and fabrication methods thereof 有权
    分离栅存储单元及其制造方法

    公开(公告)号：US20080121975A1

    公开(公告)日：2008-05-29

    申请号：US11592290

    申请日：2006-11-03

    申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

    摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。 一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。 一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

    Split-gate memory cells and fabrication methods thereof
    22.
    发明申请
    Split-gate memory cells and fabrication methods thereof 失效
    分离栅存储单元及其制造方法

    公开(公告)号：US20080105917A1

    公开(公告)日：2008-05-08

    申请号：US11785382

    申请日：2007-04-17

    申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/788 ,  H01L27/115

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.

    摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。 活动区域的顶层低于隔离区域的顶层。 一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。 一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

    Reverse connection MTJ cell for STT MRAM
    24.
    发明授权
    Reverse connection MTJ cell for STT MRAM 有权
    用于STT MRAM的反向连接MTJ单元

    公开(公告)号：US08416600B2

    公开(公告)日：2013-04-09

    申请号：US12626092

    申请日：2009-11-25

    申请人： Chun-Jung Lin ,  Yu-Jen Wang ,  Ya-Chen Kao ,  Wen-Cheng Chen ,  Ming-Te Liu

    发明人： Chun-Jung Lin ,  Yu-Jen Wang ,  Ya-Chen Kao ,  Wen-Cheng Chen ,  Ming-Te Liu

    IPC分类号： G11C11/00

    CPC分类号： H01L43/08 ,  G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/12

    摘要： Apparatus and methods are disclosed herein for a reverse-connection STT MTJ element of a MRAM to overcome the source degeneration effect when switching the magnetization of the MTJ element from the parallel to the anti-parallel direction. A memory cell of a MRAM having a reverse-connection MTJ element includes a switching device having a source, a gate, and a drain, and a reverse-connection MTJ device having a free layer, a fixed layer, and an insulator layer interposed between the free layer and the fixed layer. The free layer of the reverse-connection MTJ device is connected to the drain of the switching device and the fixed layer is connected to a bit line (BL). The reverse-connection MTJ device applies the lower IMTJ capability of the memory cell caused by the source degeneration effect to the less stringent IMTJ(AP->P) while preserving the higher IMTJ capability for the more demanding IMTJ(P->AP).

    摘要翻译： 本文公开了用于MRAM的反向连接STT MTJ元件的装置和方法，以在将MTJ元件的磁化从平行方向切换到反平行方向时克服源退化效应。 具有反向连接MTJ元件的MRAM的存储单元包括具有源极，栅极和漏极的开关器件和具有自由层，固定层和绝缘体层的反向连接MTJ器件， 自由层和固定层。 反连接MTJ器件的自由层连接到开关器件的漏极，固定层连接到位线（BL）。 反向连接MTJ设备将由源退化效应引起的存储器单元的较低IMTJ能力应用于较不严格的IMTJ（AP-> P），同时为更苛刻的IMTJ（P-> AP）保持较高的IMTJ能力。

    DOMAIN WALL ASSISTED SPIN TORQUE TRANSFER MAGNETRESISTIVE RANDOM ACCESS MEMORY STRUCTURE
    25.
    发明申请
    DOMAIN WALL ASSISTED SPIN TORQUE TRANSFER MAGNETRESISTIVE RANDOM ACCESS MEMORY STRUCTURE 有权
    域壁辅助转子扭矩传递磁阻随机访问存储器结构

    公开(公告)号：US20120068279A1

    公开(公告)日：2012-03-22

    申请号：US12884351

    申请日：2010-09-17

    申请人： Chih-Huang Lai ,  Sheng-Huang Huang ,  Kuo-Feng Huang ,  Ming-Te Liu ,  Chun-Jung Lin ,  Ya-Chen Kao ,  Wen-Cheng Chen

    发明人： Chih-Huang Lai ,  Sheng-Huang Huang ,  Kuo-Feng Huang ,  Ming-Te Liu ,  Chun-Jung Lin ,  Ya-Chen Kao ,  Wen-Cheng Chen

    IPC分类号： H01L29/82 ,  H01L21/02

    CPC分类号： H01L43/12 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1675 ,  G11C19/0808 ,  H01L27/228 ,  H01L43/08

    摘要： A semiconductor memory device includes a first ferromagnetic layer magnetically pinned and positioned within a first region of a substrate; a second ferromagnetic layer approximate the first ferromagnetic layer; and a barrier layer interposed between the first ferromagnetic layer and the first portion of the second ferromagnetic layer. The second ferromagnetic layer includes a first portion being magnetically free and positioned within the first region; a second portion magnetically pinned to a first direction and positioned within a second region of the substrate, the second region contacting the first region from a first side; and a third portion magnetically pinned to a second direction and positioned within a third region of the substrate, the third region contacting the first region from a second side.

    摘要翻译： 半导体存储器件包括磁性固定并位于衬底的第一区域内的第一铁磁层; 第二铁磁层近似第一铁磁层; 以及介于所述第一铁磁层与所述第二铁磁层的所述第一部分之间的阻挡层。 第二铁磁层包括无磁性的第一部分，并且位于第一区域内; 第二部分，磁性地固定在第一方向上并且位于所述基板的第二区域内，所述第二区域从所述第一侧面接触所述第一区域; 以及第三部分，其磁性地固定到第二方向并且位于所述基板的第三区域内，所述第三区域从所述第二侧面接触所述第一区域。

    Split-gate memory cells and fabrication methods thereof
    26.
    发明授权
    Split-gate memory cells and fabrication methods thereof 失效
    分离栅存储单元及其制造方法

    公开(公告)号：US07667261B2

    公开(公告)日：2010-02-23

    申请号：US11785382

    申请日：2007-04-17

    申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.

    摘要翻译： 分离栅存储单元及其制造方法。 分离栅存储器单元包括沿着第一方向在半导体衬底上形成的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。 活动区域的顶层低于隔离区域的顶层。 一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。 一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

    Split-gate memory cells and fabrication methods thereof
    27.
    发明授权
    Split-gate memory cells and fabrication methods thereof 有权
    分离栅存储单元及其制造方法

    公开(公告)号：US07652318B2

    公开(公告)日：2010-01-26

    申请号：US11592290

    申请日：2006-11-03

    申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

    摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。 一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。 一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

    Flash memory cell with split gate structure and method for forming the same
    28.
    发明申请
    Flash memory cell with split gate structure and method for forming the same 有权
    具有分离栅结构的闪存单元及其形成方法

    公开(公告)号：US20070205436A1

    公开(公告)日：2007-09-06

    申请号：US11368714

    申请日：2006-03-06

    申请人： Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

    发明人： Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

    IPC分类号： H01L29/76

    CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

    摘要： A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.

    摘要翻译： 分离门存储单元。 浮置栅极设置在基板上并与基板绝缘，该基板包括由形成在其中的一对隔离结构分开的有源区域。 浮栅设置在一对隔离结构之间，并且不与其上表面重叠。 盖层设置在浮动栅上。 控制栅极设置在浮动栅极的侧壁上并与其绝缘，部分地延伸到盖层的上表面。 源极区域形成在靠近浮动栅极一侧的衬底中。