公开(公告)号：US07274589B2

公开(公告)日：2007-09-25

申请号：US11318777

申请日：2005-12-28

申请人： Shinobu Asayama ,  Toshio Komuro

发明人： Shinobu Asayama ,  Toshio Komuro

IPC分类号： G11C11/00 ,  G11C8/00

CPC分类号： G11C11/413 ,  G11C8/08

摘要： An SRAM cell 1 includes inverters 10, 20, N-type FETs 32, 34, 36, 38, word lines 42, 44, bit lines 46, 48, and voltage applying circuits 50, 60. The voltage applying circuits 50, 60 apply a voltage Vdd to the word lines 42, 44 at the time of a read operation of the SRAM cell 1. The voltage applying circuits 50, 60 apply a voltage (Vdd+α) to the word lines 42, 44 at the time of a write operation of the SRAM cell 1. Here, α>0. Namely, the SRAM cell 1 is configured in such a manner that a voltage applied to word lines 42, 44 at the time of the write operation is higher than at the time of the read operation.

摘要翻译： SRAM单元1包括反相器10,20，N型FET32,34,36,38，字线42,44，位线46,48和电压施加电路50,60。 电压施加电路50,60在SRAM单元1的读取操作时对字线42,44施加电压V dd。 电压施加电路50,60在SRAM单元1的写入操作时对字线42,44施加电压（V SUB +Δ+α）。 这里，alpha> 0。 也就是说，SRAM单元1被配置成使得在写入操作时施加到字线42,44的电压高于读取操作时的电压。

公开(公告)号：US6066521A

公开(公告)日：2000-05-23

申请号：US256173

申请日：1999-02-24

申请人： Hiroaki Yokoyama ,  Toshio Komuro

发明人： Hiroaki Yokoyama ,  Toshio Komuro

IPC分类号： H01L29/41 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/8238

CPC分类号： H01L21/8249

摘要： In a method for manufacturing a BiMOS device, first and second semiconductor layers are formed on a semiconductor substrate, first and second field insulating layers are formed by using a LOCOS process on said first and second semiconductor layers, respectively. The first field insulating layer partitions a bipolar transistor area and a MOS transistor area, and the second field insulating layer is formed on a base-emitter junction region of the first semiconductor layer. Then, impurities are introduced via the second field insulating layer into the first semiconductor layer to form a base region therein. Then, an emitter opening is perforated in the second field insulating layer, and a polycrystalline silicon layer is formed on the second field insulating layer. Then, impurities of a first conductivity type are introduced into the polycrystalline silicon layer, and a heating operation is performed upon the polycrystalline silicon layer to form an emitter region. Then, the polycrystalline silicon layer is patterned to form an emitter electrode. Then, a gate insulating layer is formed on the second semiconductor layer, and a gate electrode is formed on the gate insulating layer. Finally, a base graft region is formed type in the first semiconductor layer and source/drain regions are formed in the second semiconductor layer.

摘要翻译： 在制造BiMOS器件的方法中，在半导体衬底上形成第一和第二半导体层，分别通过在所述第一和第二半导体层上使用LOCOS工艺形成第一和第二场绝缘层。 第一场绝缘层分隔双极晶体管区域和MOS晶体管区域，并且第二场绝缘层形成在第一半导体层的基极 - 发射极结区域上。 然后，通过第二场绝缘层将杂质引入第一半导体层，以在其中形成基极区域。 然后，在第二场绝缘层中穿孔发射极开口，在第二场绝缘层上形成多晶硅层。 然后，将第一导电类型的杂质引入到多晶硅层中，并且在多晶硅层上进行加热操作以形成发射极区域。 然后，对多晶硅层进行构图以形成发射电极。 然后，在第二半导体层上形成栅极绝缘层，在栅极绝缘层上形成栅电极。 最后，在第一半导体层中形成基底移植区域，在第二半导体层中形成源/漏区域。

公开(公告)号：US5933720A

公开(公告)日：1999-08-03

申请号：US840722

申请日：1997-04-25

申请人： Hiroaki Yokoyama ,  Toshio Komuro

发明人： Hiroaki Yokoyama ,  Toshio Komuro

IPC分类号： H01L29/41 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/8238

CPC分类号： H01L21/8249

摘要： In a method for manufacturing a BiMOS device, first and second semiconductor layers are formed on a semiconductor substrate, first and second field insulating layers are formed by using a LOCOS process on said first and second semiconductor layers, respectively. The first field insulating layer partitions a bipolar transistor area and a MOS transistor area, and the second field insulating layer is formed on a base-emitter junction region of the first semiconductor layer. Then, impurities are introduced via the second field insulating layer into the first semiconductor layer to form a base region therein. Then, an emitter opening is perforated in the second field insulating layer, and a polycrystalline silicon layer is formed on the second field insulating layer. Then, impurities of a first conductivity type are introduced into the polycrystalline silicon layer, and a heating operation is performed upon the polycrystalline silicon layer to form an emitter region. Then, the polycrystalline silicon layer is patterned to form an emitter electrode. Then, a gate insulating layer is formed on the second semiconductor layer, and a gate electrode is formed on the gate insulating layer. Finally, a base graft region is formed type in the first semiconductor layer and source/drain regions are formed in the second semiconductor layer.

公开(公告)号：US5780902A

公开(公告)日：1998-07-14

申请号：US764105

申请日：1996-12-06

申请人： Toshio Komuro

发明人： Toshio Komuro

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L29/10 ,  H01L29/78 ,  H01L31/113

CPC分类号： H01L29/7835 ,  H01L29/1083 ,  H01L29/66659 ,  H01L21/26586

摘要： A semiconductor device with an LDD structure type MOS transistor is fabricated by forming a gate electrode on a semiconductor layer of a first conductivity type and a source/drain region in the semiconductor layer, the source/drain region having a high impurity concentration region and a low impurity concentration region of a second conductivity type. A pocket of the first conductivity type is formed in contact with the low impurity concentration region only on a drain region side and immediately under the low concentration region of the second conductivity type. The pocket formed only on the drain side can suppress the short channel effect and also the hot carrier generation without lowering the current capacity on the source side where no pocket is present.

摘要翻译： 通过在半导体层中的第一导电类型和源极/漏极区域的半导体层上形成栅电极，具有高杂质浓度区域的源极/漏极区域和 第二导电类型的低杂质浓度区域。 第一导电类型的口袋仅在漏极区域侧和第二导电类型的低浓度区域的正下方形成与低杂质浓度区域接触。 仅在漏极侧形成的口袋可以抑制短沟道效应以及热载流子的产生，而不会降低源极侧不存在口袋的电流容量。

公开(公告)号：US5652154A

公开(公告)日：1997-07-29

申请号：US679379

申请日：1996-07-08

申请人： Toshio Komuro

发明人： Toshio Komuro

IPC分类号： H01L21/8249 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H01L21/265

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  Y10S148/009

摘要： In a method for manufacturing a "BiCMOS" semiconductor integrated circuit, a gate oxide film 110 and a polysilicon film are grown on a semiconductor substrate, and after phosphorus is doped, the polysilicon film is patterned to form gate electrodes 112a and 112b and an emitter electrode 112c. A heat treatment is performed to form an emitter diffused region 113. Phosphorus and boron are selectively implanted with a low impurity concentration, respectively, to form a LDD N.sup.- region 114 and a LDD P.sup.- region 115. Thereafter, a side wall 116 is formed, and boron is implanted into areas B and C so as to form P.sup.+ source/drain regions 117 and a graft base region 18, respectively. Phosphorus is implanted to form N.sup.+ source/drain regions 119.

摘要翻译： 在“BiCMOS”半导体集成电路的制造方法中，在半导体基板上生长栅极氧化膜110和多晶硅膜，在磷掺杂后，对多晶硅膜进行图案化，形成栅电极112a，112b，发射极 电极112c。 进行热处理以形成发射极扩散区域113.分别以低杂质浓度选择性地注入磷和硼以形成LDD N-区域114和LDD P-区域115.此后，侧壁116为 并且将硼注入到区域B和C中，以分别形成P +源极/漏极区域117和移植物基底区域18。 植入磷以形成N +源极/漏极区域119。

公开(公告)号：US5610855A

公开(公告)日：1997-03-11

申请号：US576574

申请日：1995-12-21

申请人： Toshio Komuro

发明人： Toshio Komuro

IPC分类号： G11C11/56 ,  G11C11/24

CPC分类号： G11C11/565 ,  G11C2211/5642 ,  G11C7/06

摘要： In order to provide a multi-valued DRAM with an access time comparable to ordinary binary DRAMs, a potential difference generated by a memory cell between a pair of bit-lines is delivered to N-1 sets of sense amplifiers. Each delivered potential difference is shifted by a predetermined value for each sense amplifier for classifying the potential difference into N levels. A refreshing potential for the memory cell is obtained from outputs of the sense amplifiers activated with sense amplifier activating signals having potentials predetermined for each sense amplifier.

摘要翻译： 为了提供具有与普通二进制DRAM相当的访问时间的多值DRAM，由一对位线之间的存储单元产生的电位差传送到N-1组读出放大器。 每个传送的电位差被移位每个读出放大器的预定值，用于将电位差分类为N个电平。 从具有针对每个读出放大器预定的电位的读出放大器激活信号激活的读出放大器的输出获得存储单元的刷新电位。

公开(公告)号：US5274598A

公开(公告)日：1993-12-28

申请号：US716480

申请日：1991-06-17

申请人： Takeo Fujii ,  Toshio Komuro

发明人： Takeo Fujii ,  Toshio Komuro

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/401 ,  G11C11/4097 ,  G11C11/40 ,  G11C7/00

CPC分类号： G11C11/4097 ,  G11C7/065

摘要： A semiconductor memory provided with improved sense amplifier-bit line arrangement which is suitable for a high-speed and high-sensitivity read operation. The memory comprises a main bit line pair, a main sense amplifier, a plurality of sub-bit line pairs and a plurality of sub-sense amplifiers in each column. Each of the sub-sense amplifiers includes a pair of output nodes coupled to the main bit line pair and a pair of input nodes coupled to one of the sub-bit line pairs. A pair of switch elements are inserted between the main bit line pair and each one of the sub-bit line pairs for selectively feeding an output of the main sense amplifier back to one of the sub-bit line pair selected.

公开(公告)号：US5008567A

公开(公告)日：1991-04-16

申请号：US342066

申请日：1989-04-24

申请人： Kazuo Shibata ,  Toshio Komuro

发明人： Kazuo Shibata ,  Toshio Komuro

IPC分类号： G06F13/10 ,  H03K5/00 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0944 ,  H03K19/096

CPC分类号： H03K17/162 ,  H03K19/00361 ,  H03K19/096

摘要： A signal generating circuit which generates an output signal in a dynamic manner without being influenced by noise is disclosed. The signal generating circuit comprises a first transistor connected between a power voltage source and an output node, and second and third transistors connected in series between the output node and a ground voltage line. A first signal which assumes an active level in a first period and an inactive a second period subsequent to the first period, is applied to a gate of the second transistor, and a second signal which assumes an active level for a first time duration in the second period and an inactive level in a remaining second time duration in the second period and the first period, is applied to a gate of the first transistor. A third signal which assumes an active level in the first period and an inactive level in the second time duration, is applied to a gate of the second transistor.

公开(公告)号：US4641293A

公开(公告)日：1987-02-03

申请号：US575861

申请日：1984-02-01

申请人： Toshio Komuro

发明人： Toshio Komuro

IPC分类号： G11B15/10 ,  G11B31/00 ,  H04B1/08

CPC分类号： G11B15/10 ,  G11B31/003

摘要： A cassette tape player is combined with a radio receiver and has a plurality of player control buttons used for selecting the operation mode of the tape playing mechanism and, a radio control button used for operating the radio signal receiving device, and a stop button used for stopping either the tape playing mechanism or the radio signal receiving device, wherein one of the player control buttons or radio control button can be switched and the operating condition either one of the tape playing mechanism or the radio signal receiving device can to be released by manipulating the stop button.

摘要翻译： 盒式磁带播放机与无线电接收机组合，并具有用于选择磁带播放机构的操作模式的多个播放器控制按钮，以及用于操作无线电信号接收装置的无线电控制按钮和用于 停止磁带播放机构或无线电信号接收装置，其中可以切换播放器控制按钮或无线电控制按钮中的一个，并且通过操纵可以释放磁带播放机构或无线电信号接收装置中的任一个的操作条件 停止按钮。