公开(公告)号：US20050037558A1

公开(公告)日：2005-02-17

申请号：US10643675

申请日：2003-08-15

Applicant: Yoyi Gong ,  Tony Lin ,  Jung-Tsung Tseng ,  Abula Yu

Inventor： Yoyi Gong ,  Tony Lin ,  Jung-Tsung Tseng ,  Abula Yu

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/417 ,  H01L21/4763 ,  H01L21/8234

CPC classification number: H01L29/41783 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545

Abstract: A method for fabricating a transistor having a fully silicided gate is described. A silicon substrate with a semi-finished transistor formed thereon is provided, wherein the transistor comprises a gate dielectric film, a silicon gate, a cap layer on the silicon gate, a spacer and a source/drain region. A raised source/drain is formed on the source/drain region, and then the cap layer is removed. Subsequently, a full silicidation process is performed to fully silicide the silicon gate.

公开(公告)号：US06323105B1

公开(公告)日：2001-11-27

申请号：US09188822

申请日：1998-11-09

Applicant: Coming Chen ,  Tony Lin

Inventor： Coming Chen ,  Tony Lin

IPC: H01L2176

CPC classification number: H01L21/76202 ,  H01L21/763

Abstract: A method for fabrication a shallow trench isolation (STI) structure by combining uses of a STI process and a local oxidation (LOCAS) process is provided. The method includes forming a first liner oxide layer over a substrate, on which a patterned hard material layer is formed. A hard spacer is formed on each sidewall of the hard material layer. A LOCOS structure is formed on the substrate other than the hard spacer and the hard material layer. Then, the hard spacer is removed to expose a portion of the pad oxide on the substrate. A trench is formed in the substrate on each side of the LOCOS structure. A conformal second liner oxide layer is formed on the inner surface of the trench. The trench is filled with a polysilicon layer, having a surface higher than the substrate surface. A second thermal process is performed to oxidize the polysilicon layer so as to merge the LOCOS structure to cover the surface of the polysilicon layer. The hard material layer is removed to form the isolation structure of the invention.

Abstract translation: 提供了一种通过组合STI工艺和局部氧化（LOCAS）工艺的使用来制造浅沟槽隔离（STI）结构的方法。 该方法包括在衬底上形成第一衬里氧化物层，在其上形成图案化的硬质材料层。 在硬质材料层的每个侧壁上形成有硬质隔离物。 在除了硬隔离物和硬质材料层之外的基板上形成LOCOS结构。 然后，去除硬质间隔物以暴露衬底上的衬垫氧化物的一部分。 在LOCOS结构的每一侧的基板中形成沟槽。 在沟槽的内表面上形成保形第二衬垫氧化物层。 沟槽填充有表面高于衬底表面的多晶硅层。 进行第二热处理以氧化多晶硅层，以便合并LOCOS结构以覆盖多晶硅层的表面。 去除硬质材料层以形成本发明的隔离结构。

公开(公告)号：US06297082B1

公开(公告)日：2001-10-02

申请号：US09383033

申请日：1999-08-25

Applicant: Tony Lin ,  Alice Chao ,  Jih-Wen Chou

Inventor： Tony Lin ,  Alice Chao ,  Jih-Wen Chou

IPC: H01L218238

CPC classification number: H01L29/66537 ,  H01L21/823807 ,  H01L29/7833

Abstract: A fabrication method for a metal oxide semiconductor (MOS) transistor involves forming gate oxide layers of different thicknesses on a core region and a input/output (I/O) region. After forming wells in the substrate, two implantation regions for providing a threshold voltage (VT) adjustment and an anti-punch through layer are formed respectively in a P-well and a N-well of the core region as well as a P-well and a N-well of the I/O region. The method involves forming a pattern mask on the gate oxide layer, wherein the pattern mask has an opening, which may be a channel that corresponds to the P-well of the core region. With the pattern mask serving as an ion implantation mask, two implantation regions for providing the VT adjustment and the anti-punch through layer are formed in the P-well of the core region. After the pattern mask is removed, the steps described above are repeated in order to form implantation regions in other regions, but the sequence of the steps can be swapped around at will. The subsequent process for the MOS transistor is then performed.

Abstract translation: 金属氧化物半导体（MOS）晶体管的制造方法涉及在核心区域和输入/输出（I / O）区域上形成不同厚度的栅极氧化物层。 在衬底中形成阱之后，分别在芯区的P阱和N阱以及P阱中形成用于提供阈值电压（VT）调整和抗穿通层的两个注入区域 和I / O区域的N阱。 该方法包括在栅极氧化物层上形成图案掩模，其中图案掩模具有开口，该开口可以是对应于核心区域的P阱的沟道。 利用图案掩模作为离子注入掩模，在核心区域的P阱中形成用于提供VT调整和抗穿透层的两个注入区域。 在去除图案掩模之后，重复上述步骤以在其它区域中形成植入区域，但是步骤的顺序可以随意地交换。 然后执行MOS晶体管的后续处理。

公开(公告)号：US06192093B1

公开(公告)日：2001-02-20

申请号：US09364481

申请日：1999-07-30

Applicant: Benny W H Lai ,  Tony Lin ,  Charles L. Wang

Inventor： Benny W H Lai ,  Tony Lin ,  Charles L. Wang

IPC: H04L2536

CPC classification number: H04L7/041 ,  H04J3/0602 ,  H04L25/4915

Abstract: A method and system for receiving CIMT encoded data transmitted in simplex mode. The receiver (12) is adapted to receive a stream of digital data and analyze successive portions thereof to identify a predetermined pattern of data. The receiver (12) outputs the received digital data in response to a detection of the predetermined pattern of data and, in the alternative, outputs other data in response to a failure to detect the predetermined pattern of data. In the illustrative embodiment, the stream of digital data is transmitted as conditional invert master transition encoded simplex data. The receiver (12) includes a CIMT decoder (16) which analyzes the input data to identify a master transition therein. The receiver (12) uses a local clock to analyze successive portions of the received data stream and word alignment logic to identify a master transition therein. In the best mode, the inventive teachings are implemented in a communications system having a CIMT encoder (13) which transmits a time scrambled flag bit along with a stream of CIMT encoded data. The receiver (12) descrambles the flag bit and uses it to detect the master transition therein in the presence of static data.

Abstract translation: 用于接收以单工模式发送的CIMT编码数据的方法和系统。 接收器（12）适于接收数字数据流并分析其连续部分以识别预定的数据模式。 响应于预定的数据模式的检测，接收机（12）输出接收到的数字数据，并且在另一方面，响应于检测到预定的数据模式的故障而输出其他数据。 在说明性实施例中，数字数据流作为条件反转主转换编码单纯形数据被发送。 接收器（12）包括CIMT解码器（16），其分析输入数据以识别其中的主转换。 接收器（12）使用本地时钟来分析接收到的数据流和字对齐逻辑的连续部分以识别其中的主转换。 在最佳模式中，本发明的教导在具有CIMT编码器（13）的通信系统中实现，CIMT编码器（13）与CIMT编码数据流一起发送时间加扰标志位。 接收机（12）对标志位进行解扰并使用它在静态数据的存在下检测其中的主转换。

公开(公告)号：US6133083A

公开(公告)日：2000-10-17

申请号：US218543

申请日：1998-12-22

Applicant: Tony Lin ,  Coming Chen ,  Jenn Tsao

Inventor： Tony Lin ,  Coming Chen ,  Jenn Tsao

IPC: H01L21/8242 ,  H01L21/8234 ,  H01L21/8244

CPC classification number: H01L27/10894 ,  H01L27/10888

Abstract: A method for fabricating an embedded DRAM. A substrate having a memory circuit region and a logic circuit region is provided. A first gate, a first source/drain region and a second source/drain region are formed in the memory circuit region. A second gate and a third source/drain region are formed in the logic circuit region. A first dielectric layer is formed over the substrate. In the first dielectric layer, a first contact hole is formed to expose the first source/drain region and a second contact hole is formed to expose the second gate and the third source/drain region. A bit line is formed to electrically couple with the first source/drain region through the first contact hole. A local interconnect is formed to electrically couple with the second gate and the third source/drain region through the second contact hole. A second dielectric layer is formed over the substrate. A third contact hole is formed in the first dielectric layer and the second dielectric layer to expose the second source/drain region. A capacitor is formed to electrically couple with the second source/drain region through the third contact hole.

Abstract translation: 一种用于制造嵌入式DRAM的方法。 提供具有存储电路区域和逻辑电路区域的衬底。 第一栅极，第一源极/漏极区域和第二源极/漏极区域形成在存储器电路区域中。 第二栅极和第三源极/漏极区域形成在逻辑电路区域中。 第一电介质层形成在衬底上。 在第一电介质层中，形成第一接触孔以暴露第一源极/漏极区域，并且形成第二接触孔以暴露第二栅极和第三源极/漏极区域。 形成位线，以通过第一接触孔与第一源极/漏极区域电耦合。 局部互连形成为通过第二接触孔与第二栅极和第三源极/漏极区域电耦合。 第二介质层形成在衬底上。 在第一电介质层和第二电介质层中形成第三接触孔以露出第二源/漏区。 形成电容器以通过第三接触孔与第二源极/漏极区域电耦合。

公开(公告)号：US6083827A

公开(公告)日：2000-07-04

申请号：US212084

申请日：1998-12-15

Applicant: Tony Lin ,  Coming Chen ,  Wen-Kuan Yeh

Inventor： Tony Lin ,  Coming Chen ,  Wen-Kuan Yeh

IPC: H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76895 ,  H01L21/3212 ,  H01L29/66545

Abstract: A method for fabricating a local interconnect. A gate having a gate oxide layer, a gate polysilicon layer and a cap layer is formed on a provided substrate. A spacer is formed on the sidewall of the gate, and a source/drain region is formed in the substrate. A planarized dielectric layer is formed over the substrate to expose the cap layer. A portion of the dielectric layer and the spacer on one side of the gate is removed to form an opening, so that the source/drain region is exposed. The opening is transformed into a local-interconnect opening by removing the cap layer. A local interconnect is formed by forming a conductive layer in the local-interconnect opening.

Abstract translation: 一种用于制造局部互连的方法。 在所提供的衬底上形成具有栅极氧化物层，栅极多晶硅层和覆盖层的栅极。 在栅极的侧壁上形成间隔物，在衬底中形成源/漏区。 平坦化介电层形成在衬底上以露出盖层。 电介质层的一部分和栅极一侧上的间隔物被去除以形成开口，从而暴露出源极/漏极区域。 通过去除盖层将开口转变成局部互连开口。 通过在局部互连开口中形成导电层形成局部互连。

公开(公告)号：US6077769A

公开(公告)日：2000-06-20

申请号：US72311

申请日：1998-05-04

Applicant: Yimin Huang ,  Tony Lin ,  Tri-Rung Yew

Inventor： Yimin Huang ,  Tony Lin ,  Tri-Rung Yew

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76811

Abstract: A method is provided for fabricating a dual damascene structure on a substrate with a first dielectric layer, an etching stop layer, a second dielectric layer, and a hard mask layer formed on it. The first step is to define the hard mask layer in order to form the first hole, which corresponds to the position of the conductive layer exposing the second dielectric layer. Then, an etching process, including an etching step with medium SiO.sub.2 /SiN etching selectivity and an over-etching step with high SiO.sub.2 /SiN etching selectivity, is performed to form the second hole and the third hole. Finally, a glue/barrier layer and a metal layer are filled into the second hole and the third hole, thus accomplishing a dual damascene structure.

Abstract translation: 提供了一种用于在衬底上制造双镶嵌结构的方法，其上形成有第一介电层，蚀刻停止层，第二介电层和硬掩模层。 第一步是定义硬掩模层以形成第一孔，其对应于暴露第二电介质层的导电层的位置。 然后，进行包括具有中等SiO 2 / SiN蚀刻选择性的蚀刻步骤和具有高SiO 2 / SiN蚀刻选择性的过蚀刻步骤的蚀刻工艺，以形成第二孔和第三孔。 最后，将胶/阻挡层和金属层填充到第二孔和第三孔中，从而实现双镶嵌结构。

公开(公告)号：US6015746A

公开(公告)日：2000-01-18

申请号：US056530

申请日：1998-04-07

Applicant: Wen-Kuan Yeh ,  Tony Lin ,  Heng-Sheng Huang

Inventor： Wen-Kuan Yeh ,  Tony Lin ,  Heng-Sheng Huang

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66583 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/665

Abstract: A method of fabricating a semiconductor device. On a semiconductor substrate comprising a device isolation structure and an active region isolated by the device isolation region, an oxide layer is formed and etched on the active region to form an opening, so that the active within the opening is exposed. A first spacer is formed on a side wall of the opening. A gate oxide layer is formed on the active region within the opening. A conductive layer is formed on the gate oxide layer, so that the opening is filled thereby. The oxide layer is removed. The exposed active region is lightly doped to form a lightly doped region by using the conductive layer and the first spacer as a mask. A second spacer is formed on a side wall of the first spacer and leaves a portion of the first spacer to be exposed. The exposed active region is heavily doped to form a source/drain region by using the conductive layer, the first spacer, and the second spacer as a mask. The first spacer is removed to define a gate, so that an air gap between the gate and the second spacer is formed.

Abstract translation: 一种制造半导体器件的方法。 在包括器件隔离结构和由器件隔离区隔离的有源区的半导体衬底上，在有源区上形成氧化层并蚀刻以形成开口，从而露出开口内的活性物质。 第一间隔件形成在开口的侧壁上。 栅极氧化层形成在开口内的有源区上。 在栅极氧化物层上形成导电层，从而填充开口。 去除氧化物层。 通过使用导电层和第一间隔物作为掩模，暴露的有源区域被轻掺杂以形成轻掺杂区域。 第二间隔件形成在第一间隔件的侧壁上并且留下待暴露的第一间隔件的一部分。 通过使用导电层，第一间隔件和第二间隔件作为掩模，暴露的有源区域被重掺杂以形成源极/漏极区域。 去除第一间隔物以限定栅极，从而形成栅极和第二间隔物之间​​的气隙。

公开(公告)号：US5950090A

公开(公告)日：1999-09-07

申请号：US193217

申请日：1998-11-16

Applicant: Coming Chen ,  Tony Lin ,  Jih-Wen Chou

Inventor： Coming Chen ,  Tony Lin ,  Jih-Wen Chou

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/417

CPC classification number: H01L29/6659 ,  H01L21/28061 ,  H01L21/76224 ,  H01L29/66545 ,  H01L29/41775

Abstract: A method for fabricating a MOS transistor device is provided. The method contains sequentially forming an oxide layer, a polysilicon layer, and a cap layer over a semiconductor substrate. Patterning the oxide layer, the polysilicon layer, the cap layer, and the substrate forms a trench opening in the substrate. A shallow trench isolation (STI) structure is formed by filling the opening with insulating material. A first-stage gate structure is formed on the substrate by patterning the oxide layer, the polysilicon layer, and the cap layer. A top portion of the STI structure above the substrate surface is exposed. A light ion implantation is performed to form a lightly doped region. Several spacers are respectively formed on each sidewall of the first-stage gate structure and each exposed sidewall of the STI structure. A heavy ion implantation process is performed to form interchangeable source/drain regions at each side of the first-stage gate structure. The cap layer is removed to leave an opening. A conductive layer is formed over the substrate and is planarized so that a remaining portion of the conductive layer fills the opening to serve as a gate metal layer. The remaining portion of the conductive layer also fills a free space between the spacers above the interchangeable source/drain regions to form several contact plugs. A dielectric layer is formed over the substrate with second contact plugs, respectively electrically coupled to the gate metal layer and the first contact plugs.

Abstract translation: 提供一种用于制造MOS晶体管器件的方法。 该方法包括在半导体衬底上顺序形成氧化物层，多晶硅层和覆盖层。 对氧化物层，多晶硅层，盖层和衬底进行图案化，在衬底中形成沟槽开口。 通过用绝缘材料填充开口形成浅沟槽隔离（STI）结构。 通过图案化氧化物层，多晶硅层和盖层，在衬底上形成第一级栅极结构。 暴露基板表面上方的STI结构的顶部。 进行轻离子注入以形成轻掺杂区域。 在STI结构的第一级栅极结构的每个侧壁和每个暴露的侧壁上分别形成几个间隔物。 执行重离子注入工艺以在第一级栅极结构的每一侧形成可互换的源/漏区。 盖层去除以留下开口。 导电层形成在衬底上并被平坦化，使得导电层的剩余部分填充开口以用作栅极金属层。 导电层的剩余部分还填充可互换的源极/漏极区之间的间隔物之间​​的自由空间，以形成多个接触插塞。 在基板上形成介电层，第二接触插塞分别电耦合到栅极金属层和第一接触插塞。

公开(公告)号：US08419845B2

公开(公告)日：2013-04-16

申请号：US13194734

申请日：2011-07-29

Applicant: Tony Lin

Inventor： Tony Lin

IPC: B01D46/00

CPC classification number: B01D46/12 ,  B01D46/0023 ,  B01D2273/30 ,  F24F2001/0096

Abstract: The present invention provides an air filter including a main body, a pressure fan, a filter mode and a fixing assembly. The main body has a containing room, an entrance hole and an exit hole. The pressure fan is disposed in the containing room. The filter mode includes a first filter layer, a second filter layer and a frame body. The first filter layer is disposed in the entrance hole, and the second filter layer is disposed in the frame body. As such, users can select to use only the first filter layer or both filter layers at one time. Moreover, users only need to let the frame body pivot to a position away from the entrance hole so that users can change the filter layers faster and easier.

Abstract translation: 本发明提供一种空气过滤器，包括主体，压力风扇，过滤器模式和定影组件。 主体有收容室，入口孔和出口孔。 压力风扇设置在容纳室内。 滤波器模式包括第一滤波器层，第二滤波器层和框架体。 第一过滤层设置在入口孔中，第二过滤层设置在框体内。 因此，用户可以一次选择仅使用第一过滤层或两个过滤层。 而且，用户只需要让框架体转动到远离入口孔的位置，以便用户可以更快，更容易地更换过滤器层。