公开(公告)号：US6117743A

公开(公告)日：2000-09-12

申请号：US203023

申请日：1998-12-01

Applicant: Wen-Kuan Yeh ,  Tony Lin ,  Coming Chen

Inventor： Wen-Kuan Yeh ,  Tony Lin ,  Coming Chen

IPC: H01L21/027 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L29/66575 ,  H01L21/0276 ,  H01L21/28061 ,  H01L21/28123 ,  H01L29/4941 ,  H01L29/66545 ,  Y10S438/952

Abstract: A method of manufacturing MOS device including the steps of providing a semiconductor substrate that has a device isolation structure thereon, and then depositing a gate oxide layer, a polysilicon layer and an anti-reflection coating in sequence over the substrate. Next, a gate structure is patterned out of the gate oxide layer, the polysilicon layer and the anti-reflection coating. Then, spacers are formed on the sidewalls of the gate structure. Thereafter, a metal silicide layer is formed over source/drain regions. After that, an inter-layer dielectric (ILD) layer is formed over the gate structure and the entire substrate. Then, the inter-layer dielectric layer is planarized to expose the anti-reflection coating. Next, the anti-reflection coating is removed, and then a barrier layer is deposited over the inter-layer dielectric layer and the polysilicon layer. Subsequently, a conductive layer is deposited over the barrier layer. Finally, a chemical-mechanical polishing operation is carried out to planarize the conductive layer, retaining only the conductive layer above the polysilicon layer.

Abstract translation: 一种制造MOS器件的方法，包括以下步骤：提供在其上具有器件隔离结构的半导体衬底，然后在衬底上依次沉积栅极氧化物层，多晶硅层和抗反射涂层。 接下来，栅极结构从栅极氧化物层，多晶硅层和抗反射涂层构图。 然后，在栅极结构的侧壁上形成间隔物。 此后，在源极/漏极区域上形成金属硅化物层。 之后，在栅极结构和整个衬底上形成层间介电层（ILD）层。 然后，层间电介质层被平坦化以暴露抗反射涂层。 接下来，去除防反射涂层，然后在层间电介质层和多晶硅层上沉积阻挡层。 随后，在阻挡层上沉积导电层。 最后，进行化学机械抛光操作以使导电层平坦化，仅在多晶硅层上保留导电层。

公开(公告)号：US06323105B1

公开(公告)日：2001-11-27

申请号：US09188822

申请日：1998-11-09

Applicant: Coming Chen ,  Tony Lin

Inventor： Coming Chen ,  Tony Lin

IPC: H01L2176

CPC classification number: H01L21/76202 ,  H01L21/763

Abstract: A method for fabrication a shallow trench isolation (STI) structure by combining uses of a STI process and a local oxidation (LOCAS) process is provided. The method includes forming a first liner oxide layer over a substrate, on which a patterned hard material layer is formed. A hard spacer is formed on each sidewall of the hard material layer. A LOCOS structure is formed on the substrate other than the hard spacer and the hard material layer. Then, the hard spacer is removed to expose a portion of the pad oxide on the substrate. A trench is formed in the substrate on each side of the LOCOS structure. A conformal second liner oxide layer is formed on the inner surface of the trench. The trench is filled with a polysilicon layer, having a surface higher than the substrate surface. A second thermal process is performed to oxidize the polysilicon layer so as to merge the LOCOS structure to cover the surface of the polysilicon layer. The hard material layer is removed to form the isolation structure of the invention.

Abstract translation: 提供了一种通过组合STI工艺和局部氧化（LOCAS）工艺的使用来制造浅沟槽隔离（STI）结构的方法。 该方法包括在衬底上形成第一衬里氧化物层，在其上形成图案化的硬质材料层。 在硬质材料层的每个侧壁上形成有硬质隔离物。 在除了硬隔离物和硬质材料层之外的基板上形成LOCOS结构。 然后，去除硬质间隔物以暴露衬底上的衬垫氧化物的一部分。 在LOCOS结构的每一侧的基板中形成沟槽。 在沟槽的内表面上形成保形第二衬垫氧化物层。 沟槽填充有表面高于衬底表面的多晶硅层。 进行第二热处理以氧化多晶硅层，以便合并LOCOS结构以覆盖多晶硅层的表面。 去除硬质材料层以形成本发明的隔离结构。

公开(公告)号：US6133083A

公开(公告)日：2000-10-17

申请号：US218543

申请日：1998-12-22

Applicant: Tony Lin ,  Coming Chen ,  Jenn Tsao

Inventor： Tony Lin ,  Coming Chen ,  Jenn Tsao

IPC: H01L21/8242 ,  H01L21/8234 ,  H01L21/8244

CPC classification number: H01L27/10894 ,  H01L27/10888

Abstract: A method for fabricating an embedded DRAM. A substrate having a memory circuit region and a logic circuit region is provided. A first gate, a first source/drain region and a second source/drain region are formed in the memory circuit region. A second gate and a third source/drain region are formed in the logic circuit region. A first dielectric layer is formed over the substrate. In the first dielectric layer, a first contact hole is formed to expose the first source/drain region and a second contact hole is formed to expose the second gate and the third source/drain region. A bit line is formed to electrically couple with the first source/drain region through the first contact hole. A local interconnect is formed to electrically couple with the second gate and the third source/drain region through the second contact hole. A second dielectric layer is formed over the substrate. A third contact hole is formed in the first dielectric layer and the second dielectric layer to expose the second source/drain region. A capacitor is formed to electrically couple with the second source/drain region through the third contact hole.

Abstract translation: 一种用于制造嵌入式DRAM的方法。 提供具有存储电路区域和逻辑电路区域的衬底。 第一栅极，第一源极/漏极区域和第二源极/漏极区域形成在存储器电路区域中。 第二栅极和第三源极/漏极区域形成在逻辑电路区域中。 第一电介质层形成在衬底上。 在第一电介质层中，形成第一接触孔以暴露第一源极/漏极区域，并且形成第二接触孔以暴露第二栅极和第三源极/漏极区域。 形成位线，以通过第一接触孔与第一源极/漏极区域电耦合。 局部互连形成为通过第二接触孔与第二栅极和第三源极/漏极区域电耦合。 第二介质层形成在衬底上。 在第一电介质层和第二电介质层中形成第三接触孔以露出第二源/漏区。 形成电容器以通过第三接触孔与第二源极/漏极区域电耦合。

公开(公告)号：US6083827A

公开(公告)日：2000-07-04

申请号：US212084

申请日：1998-12-15

Applicant: Tony Lin ,  Coming Chen ,  Wen-Kuan Yeh

Inventor： Tony Lin ,  Coming Chen ,  Wen-Kuan Yeh

IPC: H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76895 ,  H01L21/3212 ,  H01L29/66545

Abstract: A method for fabricating a local interconnect. A gate having a gate oxide layer, a gate polysilicon layer and a cap layer is formed on a provided substrate. A spacer is formed on the sidewall of the gate, and a source/drain region is formed in the substrate. A planarized dielectric layer is formed over the substrate to expose the cap layer. A portion of the dielectric layer and the spacer on one side of the gate is removed to form an opening, so that the source/drain region is exposed. The opening is transformed into a local-interconnect opening by removing the cap layer. A local interconnect is formed by forming a conductive layer in the local-interconnect opening.

Abstract translation: 一种用于制造局部互连的方法。 在所提供的衬底上形成具有栅极氧化物层，栅极多晶硅层和覆盖层的栅极。 在栅极的侧壁上形成间隔物，在衬底中形成源/漏区。 平坦化介电层形成在衬底上以露出盖层。 电介质层的一部分和栅极一侧上的间隔物被去除以形成开口，从而暴露出源极/漏极区域。 通过去除盖层将开口转变成局部互连开口。 通过在局部互连开口中形成导电层形成局部互连。

公开(公告)号：US5950090A

公开(公告)日：1999-09-07

申请号：US193217

申请日：1998-11-16

Applicant: Coming Chen ,  Tony Lin ,  Jih-Wen Chou

Inventor： Coming Chen ,  Tony Lin ,  Jih-Wen Chou

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/417

CPC classification number: H01L29/6659 ,  H01L21/28061 ,  H01L21/76224 ,  H01L29/66545 ,  H01L29/41775

Abstract: A method for fabricating a MOS transistor device is provided. The method contains sequentially forming an oxide layer, a polysilicon layer, and a cap layer over a semiconductor substrate. Patterning the oxide layer, the polysilicon layer, the cap layer, and the substrate forms a trench opening in the substrate. A shallow trench isolation (STI) structure is formed by filling the opening with insulating material. A first-stage gate structure is formed on the substrate by patterning the oxide layer, the polysilicon layer, and the cap layer. A top portion of the STI structure above the substrate surface is exposed. A light ion implantation is performed to form a lightly doped region. Several spacers are respectively formed on each sidewall of the first-stage gate structure and each exposed sidewall of the STI structure. A heavy ion implantation process is performed to form interchangeable source/drain regions at each side of the first-stage gate structure. The cap layer is removed to leave an opening. A conductive layer is formed over the substrate and is planarized so that a remaining portion of the conductive layer fills the opening to serve as a gate metal layer. The remaining portion of the conductive layer also fills a free space between the spacers above the interchangeable source/drain regions to form several contact plugs. A dielectric layer is formed over the substrate with second contact plugs, respectively electrically coupled to the gate metal layer and the first contact plugs.

Abstract translation: 提供一种用于制造MOS晶体管器件的方法。 该方法包括在半导体衬底上顺序形成氧化物层，多晶硅层和覆盖层。 对氧化物层，多晶硅层，盖层和衬底进行图案化，在衬底中形成沟槽开口。 通过用绝缘材料填充开口形成浅沟槽隔离（STI）结构。 通过图案化氧化物层，多晶硅层和盖层，在衬底上形成第一级栅极结构。 暴露基板表面上方的STI结构的顶部。 进行轻离子注入以形成轻掺杂区域。 在STI结构的第一级栅极结构的每个侧壁和每个暴露的侧壁上分别形成几个间隔物。 执行重离子注入工艺以在第一级栅极结构的每一侧形成可互换的源/漏区。 盖层去除以留下开口。 导电层形成在衬底上并被平坦化，使得导电层的剩余部分填充开口以用作栅极金属层。 导电层的剩余部分还填充可互换的源极/漏极区之间的间隔物之间​​的自由空间，以形成多个接触插塞。 在基板上形成介电层，第二接触插塞分别电耦合到栅极金属层和第一接触插塞。

公开(公告)号：US06274450B1

公开(公告)日：2001-08-14

申请号：US09398733

申请日：1999-09-17

Applicant: Tony Lin ,  Coming Chen ,  Jih-Wen Chou

Inventor： Tony Lin ,  Coming Chen ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for manufacturing metal oxide semiconductor field effect transistor is disclosed. The metal oxide semiconductor field effect transistor is formed by a specific fabricating process that disadvantages of thermal damage are effectively prevented. According to the method, first a substrate is provided. Second, an isolation and a well are formed in the substrate, and then a first dielectric layer, a conductive layer and an anti-reflection coating layer are formed on the substrate sequentially. Third, a gate is formed on the substrate, and then a source and a drain are formed in the substrate and a spacer is formed on the substrate. Fourth, both source and drain are annealed, and then a first salicide is formed on both source and drain. Fifth, a second dielectric layer is formed on the substrate and is planarized, where the anti-reflecting coating layer is totally removed and the conductive layer is partially removed. Sixth, a second salicide is formed on the conductive layer. Seventh, the spacer is removed and both a halo and a source drain extension are formed in substrate. Finally, a third dielectric layer is formed on second dielectric layer. Obviously, one main characteristic of the invention is both source drain extension and halo are formed after a plurality of thermal processes such as deposition, annealing and formation of salicide.

Abstract translation: 公开了一种用于制造金属氧化物半导体场效应晶体管的方法。 金属氧化物半导体场效应晶体管通过具体的制造工艺形成，有效地防止了热损伤的缺点。 根据该方法，首先提供基板。 第二，在衬底中形成隔离和阱，然后依次在衬底上形成第一介电层，导电层和抗反射涂层。 第三，在衬底上形成栅极，然后在衬底中形成源极和漏极，并在衬底上形成间隔物。 第四，源极和漏极都被退火，然后在源极和漏极上形成第一自对准硅化物。 第五，在基板上形成第二电介质层并进行平面化处理，其中防反射涂层被完全去除并且导电层被部分去除。 第六，在导电层上形成第二个自对准硅化物。 第七，去除间隔物，并且在衬底中形成卤素和源极漏极延伸。 最后，在第二电介质层上形成第三电介质层。 显然，本发明的一个主要特征是源极漏极延伸，并且在诸如沉积，退火和形成硅化物的多个热处理之后形成卤素。

公开(公告)号：US06187645B1

公开(公告)日：2001-02-13

申请号：US09233354

申请日：1999-01-19

Applicant: Tony Lin ,  Coming Chen ,  Jih-Wen Chou

Inventor： Tony Lin ,  Coming Chen ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/28035

Abstract: A method for manufacturing semiconductor device. The method includes the steps of providing a substrate that has a gate structure thereon, and then forming offset spacers on the sidewalls of the gate structure. Thereafter, a thin oxide annealing operation is conducted, and then a first ion implantation is carried out using the gate structure and the offset spacers as a mask to form lightly doped drain regions in the substrate. Subsequently, secondary spacers are formed on the exterior sidewalls of the offset spacers. Finally, a second ion implantation is carried out using the gate structure, the offset spacers and the secondary spacers as a mask to form source/drain regions within the lightly doped drain regions.

Abstract translation: 一种半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底，然后在栅极结构的侧壁上形成偏置间隔物。 此后，进行薄氧化物退火操作，然后使用栅极结构和偏移间隔物作为掩模进行第一离子注入，以在衬底中形成轻掺杂的漏极区。 随后，在偏置间隔物的外侧壁上形成二次间隔物。 最后，使用栅极结构，偏移间隔物和次级间隔物作为掩模进行第二离子注入，以在轻掺杂漏极区内形成源/漏区。

公开(公告)号：US06177336B1

公开(公告)日：2001-01-23

申请号：US09187245

申请日：1998-11-06

Applicant: Tony Lin ,  Wen-Kuan Yeh ,  Coming Chen ,  Jih-Wen Chou

Inventor： Tony Lin ,  Wen-Kuan Yeh ,  Coming Chen ,  Jih-Wen Chou

IPC: H01L214763

CPC classification number: H01L29/66545 ,  H01L29/66537

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is provided. The method has steps of sequentially forming an oxide layer, a polysilicon layer and a cap layer on a semiconductor substrate to form a first-stage gate. An interchangeable source/drain region with a lightly doped drain (LDD) structure is formed in the substrate at each side of the first-stage gate. An insulating layer is formed over the substrate, and is planarized so as to exposed the cap layer. Removing the exposed cap layer forms an opening that exposes the polysilicon layer. Using the insulating layer as a mask, a self-aligned selective local implantation process is performed to form a threshold-voltage doped region and an anti-punch-through doped region below the oxide layer in the substrate. A conductive layer is formed over the substrate to fill the opening. A chemical mechanical polishing process is performed to expose the insulating layer so that a remaining portion of the conductive layer fills the opening to form together with the polysilicon layer and the oxide layer to serve as an gate structure.

Abstract translation: 提供一种制造金属氧化物半导体（MOS）晶体管的方法。 该方法具有在半导体衬底上依次形成氧化物层，多晶硅层和覆盖层以形成第一级栅极的步骤。 在第一级栅极的每一侧的衬底中形成具有轻掺杂漏极（LDD）结构的可互换的源极/漏极区域。 绝缘层形成在衬底上，并被平坦化以使盖层露出。 去除暴露的盖层形成暴露多晶硅层的开口。 使用绝缘层作为掩模，执行自对准选择性局部注入工艺以在衬底中的氧化物层下方形成阈值电压掺杂区域和抗穿通掺杂区域。 导电层形成在衬底上以填充开口。 执行化学机械抛光工艺以暴露绝缘层，使得导电层的剩余部分填充开口以与多晶硅层和氧化物层一起形成以用作栅极结构。

公开(公告)号：US06174778B1

公开(公告)日：2001-01-16

申请号：US09212055

申请日：1998-12-15

Applicant: Coming Chen ,  Tony Lin ,  Jih-Wen Chou

Inventor： Coming Chen ,  Tony Lin ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083

Abstract: A method of fabricating a metal oxide semiconductor includes formation of a gate on a substrate. A source/drain extension is formed beside the gate in the substrate. An ion implantation step is performed to implant heavy impurities with a low diffusion coefficient in the substrate. A heavily doped halo region is formed in the substrate below the source/drain extension. A tilt-angled halo implantation step is performed to form a halo-implanted region in the substrate to the side of the source/drain extension below the gate.

Abstract translation: 制造金属氧化物半导体的方法包括在基板上形成栅极。 在衬底的栅极旁边形成源极/漏极延伸部。 进行离子注入步骤以在衬底中植入具有低扩散系数的重杂质。 在源极/漏极延伸部下方的衬底中形成重掺杂的卤素区域。 进行倾斜角度的晕圈注入步骤以在衬底中的栅极下方的源极/漏极延伸侧形成卤素注入区域。

公开(公告)号：US20070259503A1

公开(公告)日：2007-11-08

申请号：US11777291

申请日：2007-07-13

Applicant: Hui-Chen Chang ,  Tony Lin ,  Brook Hsu ,  Cyrus LW Chen ,  Meng-Lin Lee ,  Wei-Tsun Shiau

Inventor： Hui-Chen Chang ,  Tony Lin ,  Brook Hsu ,  Cyrus LW Chen ,  Meng-Lin Lee ,  Wei-Tsun Shiau

IPC: H01L21/336

CPC classification number: H01L21/28114 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method of fabricating a semiconductor device is provided herein. The semiconductor device includes a substrate, a gate dielectric layer, a gate, a pair of source/drain regions and a stressed layer. The gate dielectric layer is disposed on the substrate and the gate whose top area is larger than its bottom area is disposed on the gate dielectric layer. The source/drain regions are disposed in the substrate next to the sidewalls of the gate. The stressed layer is disposed on the substrate to cover the gate and the source/drain regions.

Abstract translation: 本发明提供一种制造半导体器件的方法。 半导体器件包括衬底，栅介质层，栅极，一对源/漏区和应力层。 栅极电介质层设置在基板上，并且顶部区域大于其底部区域的栅极设置在栅极介电层上。 源极/漏极区域设置在邻近栅极的侧壁的衬底中。 应力层设置在基板上以覆盖栅极和源极/漏极区域。