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21.发明授权Boosted voltage generating circuit and semiconductor memory device having the same 失效升压电压发生电路和具有该电压产生电路的半导体存储器件公开(公告)号：US07180796B2
公开(公告)日：2007-02-20
申请号：US11269697
申请日：2005-11-09
申请人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
发明人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
IPC分类号： G11C5/14
摘要： There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
摘要翻译： 提供了一种升压电压发生电路和具有升压电压产生电路的半导体存储器件，该升压电压产生电路包括用于输出通过升高电源电压而获得的高电压的升压电路，提供高电压的调节器电路，用于产生电压 值小于高电压值，并且基于工作时间的高电压可变地设置为至少两个值，以及连接到升压电路和调节器电路的均衡器电路，用于使输出节点短路 和所述调节器电路的输出节点响应于第一控制信号，其中所述调节器电路的操作周期和所述均衡器电路的短路操作周期彼此不重叠。
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公开(公告)号：US06996024B2
公开(公告)日：2006-02-07
申请号：US10866131
申请日：2004-06-14
申请人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
发明人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
IPC分类号： G11C11/00
摘要： There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
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公开(公告)号：US20050002252A1
公开(公告)日：2005-01-06
申请号：US10896701
申请日：2004-07-22
申请人： Yoshinori Takano , Shigeru Atsumi , Toru Tanzawa
发明人： Yoshinori Takano , Shigeru Atsumi , Toru Tanzawa
摘要： A semiconductor memory device comprises memory cell array, a sense amp, and a reference voltage generator. The reference voltage generator includes a reference cell unit containing a reference cell to flow a reference current and a first current source load to supply a current to the reference cell; a reference transistor unit containing a reference transistor to flow a current reflecting the reference current and a second current source load to supply a current to the reference transistor; a control amp for negative feedback control of the reference transistor; a current source transistor; and a third current source load connected to a reference sense line.
摘要翻译： 半导体存储器件包括存储单元阵列，感测放大器和参考电压发生器。 参考电压发生器包括参考单元单元，其包含用于流过参考电流的参考单元和第一电流源负载以向参考单元提供电流; 参考晶体管单元，其包含用于流过反映参考电流的电流的参考晶体管和第二电流源负载以向参考晶体管提供电流; 用于参考晶体管的负反馈控制的控制放大器; 电流源晶体管; 以及连接到参考感测线的第三电流源负载。
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公开(公告)号：US06826068B1
公开(公告)日：2004-11-30
申请号：US10654463
申请日：2003-09-03
申请人： Hitoshi Shiga , Yoshinori Takano , Toru Tanzawa , Shigeru Atsumi
发明人： Hitoshi Shiga , Yoshinori Takano , Toru Tanzawa , Shigeru Atsumi
IPC分类号： G11C506
CPC分类号： G11C7/1021 , G11C8/10
摘要： A semiconductor integrated circuit device includes first to fourth bit lines and a redundant bit line, first to fourth column gate transistors and a redundant column gate transistor coupled to each of the first to fourth bit lines and the redundant bit lines, first to fourth column select lines and a redundant column select line coupled to each of the first to fourth column gate transistors and the redundant column gate transistor. The second column select line passes through the first bit line. The third column select line passes through the first and second bit lines. The fourth column select line passes through the first, second and third bit lines. The redundant column select line passes through the first, second, third and fourth bit lines.
摘要翻译： 半导体集成电路器件包括第一至第四位线和冗余位线，第一至第四列栅极晶体管和耦合到第一至第四位线和冗余位线中的每一个的冗余列栅极晶体管，第一至第四列选择 线路以及耦合到第一至第四列栅极晶体管和冗余列栅极晶体管中的每一个的冗余列选择线。 第二列选择线通过第一位线。 第三列选择线通过第一和第二位线。 第四列选择线通过第一，第二和第三位线。 冗余列选择线通过第一，第二，第三和第四位线。
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公开(公告)号：US07203120B2
公开(公告)日：2007-04-10
申请号：US11269696
申请日：2005-11-09
申请人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
发明人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
IPC分类号： G11C5/14
摘要： There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
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公开(公告)号：US20060055453A1
公开(公告)日：2006-03-16
申请号：US11269697
申请日：2005-11-09
申请人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
发明人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
IPC分类号： G05F1/10
摘要： There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
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27.发明授权Nonvolatile semiconductor memory having page mode with a plurality of banks 失效具有多个存储体的页面模式的非易失性半导体存储器公开(公告)号：US06795352B2
公开(公告)日：2004-09-21
申请号：US10703005
申请日：2003-11-05
申请人： Toru Tanzawa , Shigeru Atsumi , Akira Umezawa , Tadayuki Taura , Hitoshi Shiga , Yoshinori Takano
发明人： Toru Tanzawa , Shigeru Atsumi , Akira Umezawa , Tadayuki Taura , Hitoshi Shiga , Yoshinori Takano
IPC分类号： G11C1604
CPC分类号： G11C16/0408 , G11C16/08 , G11C16/26 , G11C29/70
摘要： The semiconductor memory comprises a reference current generator, first and second current converters, sense amplifiers for read, and sense amplifiers for verify. The reference current generator generates a first voltage dependent upon the current flowing through a reference cell. The first current converters, to which the first voltage is input, each generate a second voltage. The second current converters, to which the first voltage is input, each generate a third voltage. The sense amplifiers for read output data of a selection memory cell, comparing the voltage of the data-line for read with the second voltage. The sense amplifiers for verify output verify data of the selection memory cell, comparing the voltage of the data-lines for verify and the third voltage.
摘要翻译： 半导体存储器包括参考电流发生器，第一和第二电流转换器，用于读出的读出放大器和用于验证的读出放大器。 参考电流发生器根据流过参考单元的电流产生第一电压。 输入第一电压的第一电流转换器各自产生第二电压。 第一电压输入的第二电流转换器各自产生第三电压。 读出放大器，用于选择存储器单元的读取输出数据，将用于读取的数据线的电压与第二电压进行比较。 用于验证输出的读出放大器验证选择存储单元的数据，比较用于验证的数据线的电压和第三电压。
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28.发明授权Boosted voltage generating circuit and semiconductor memory device having the same 失效升压电压发生电路和具有该电压产生电路的半导体存储器件公开(公告)号：US06771547B2
公开(公告)日：2004-08-03
申请号：US10464462
申请日：2003-06-19
申请人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
发明人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
IPC分类号： G11C700
摘要： There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
摘要翻译： 提供了一种升压电压发生电路和具有升压电压产生电路的半导体存储器件，该升压电压产生电路包括用于输出通过升高电源电压而获得的高电压的升压电路，提供高电压的调节器电路，用于产生电压 值小于高电压值，并且基于工作时间的高电压可变地设置为至少两个值，以及连接到升压电路和调节器电路的均衡器电路，用于使输出节点短路 和所述调节器电路的输出节点响应于第一控制信号，其中所述调节器电路的操作周期和所述均衡器电路的短路操作周期彼此不重叠。
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公开(公告)号：US06693818B2
公开(公告)日：2004-02-17
申请号：US10376848
申请日：2003-02-28
申请人： Hitoshi Shiga , Yoshinori Takano , Toru Tanzawa , Shigeru Atsumi
发明人： Hitoshi Shiga , Yoshinori Takano , Toru Tanzawa , Shigeru Atsumi
IPC分类号： G11C506
CPC分类号： G11C7/1021 , G11C8/10
摘要： A semiconductor integrated circuit includes first to eighth column selection transistors and ninth to twelfth column selection transistors. The ninth column selection transistor is connected to the first and second column selection transistors. The tenth column selection transistor is connected to the third and fourth column selection transistors. The eleventh column selection transistor is connected to the fifth and sixth column selection transistors. The twelfth column selection transistor is connected to the seventh and eighth column selection transistors. A first column selection line is connected to gates of the first, third, fifth and seventh column selection transistors. A second column selection line is connected to gates of the second, fourth, sixth and eighth column selection transistors. Third to sixth column selection lines are connected to gates of the ninth to twelfth column selection transistors, respectively.
摘要翻译： 半导体集成电路包括第一至第八列选择晶体管和第九至第十十列选择晶体管。 第九列选择晶体管连接到第一和第二列选择晶体管。 第十列选择晶体管连接到第三和第四列选择晶体管。 第十列选择晶体管连接到第五和第六列选择晶体管。 第十二列选择晶体管连接到第七和第八列选择晶体管。 第一列选择线连接到第一，第三，第五和第七列选择晶体管的栅极。 第二列选择线连接到第二，第四，第六和第八列选择晶体管的栅极。 第三至第六列选择线分别连接到第九至第十二列选择晶体管的栅极。
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公开(公告)号：US06605986B2
公开(公告)日：2003-08-12
申请号：US10265727
申请日：2002-10-08
申请人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
发明人： Toru Tanzawa , Takeshi Miyaba , Shigeru Atsumi
IPC分类号： G05F302
摘要： There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.
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