公开(公告)号：US07439587B2

公开(公告)日：2008-10-21

申请号：US11677956

申请日：2007-02-22

申请人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

发明人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

摘要翻译： 在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。 电源线（21）形成在隔离绝缘膜（5）的上方。 在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。 换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面 ）。 利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。

公开(公告)号：US20070132028A1

公开(公告)日：2007-06-14

申请号：US11677951

申请日：2007-02-22

申请人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

发明人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

公开(公告)号：US06914307B2

公开(公告)日：2005-07-05

申请号：US10657068

申请日：2003-09-09

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Hideki Naruoka ,  Nobuyoshi Hattori ,  Shigeto Maegawa ,  Yasuo Yamaguchi ,  Takuji Matsumoto

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Hideki Naruoka ,  Nobuyoshi Hattori ,  Shigeto Maegawa ,  Yasuo Yamaguchi ,  Takuji Matsumoto

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/12 ,  H01L29/45 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L21/76286 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458

摘要： A semiconductor device includes a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, semiconductor elements being electrically isolated from each other by the isolation film. The semiconductor device also includes a PN junction portion provided under the isolation film and formed by two semiconductor regions of different conductivity types in the semiconductor layer. The isolation film includes a nitride film provided in a position corresponding to a top of the PN junction portion and has a substantially uniform thickness across the two semiconductor regions and an upper oxide film and a lower oxide film which are provided in upper and lower portions of the nitride film. The surface of the semiconductor layer is silicidized in such a state that a surface of the isolation film is exposed.

摘要翻译： 半导体器件包括半导体层，形成在半导体层上的多个半导体元件和设置在半导体层的表面中的隔离膜，半导体元件通过隔离膜彼此电隔离。 半导体器件还包括设置在隔离膜下方并由半导体层中由不同导电类型的两个半导体区域形成的PN结部分。 隔离膜包括设置在与PN结部分的顶部相对应的位置的氮化物膜，并且在两个半导体区域上具有基本上均匀的厚度，以及设置在上部和下部的上部氧化物膜和低级氧化物膜 氮化膜。 半导体层的表面在隔离膜的表面露出的状态下被硅化。

公开(公告)号：US06563172B2

公开(公告)日：2003-05-13

申请号：US09770388

申请日：2001-01-29

申请人： Yoshiko Yoshida ,  Hideki Naruoka ,  Yasuhiro Kimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

发明人： Yoshiko Yoshida ,  Hideki Naruoka ,  Yasuhiro Kimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

IPC分类号： H01L2701

CPC分类号： H01L21/7624 ,  H01L21/3105 ,  H01L21/31155

摘要： An object is to provide a semiconductor substrate processing method and a semiconductor substrate that prevent formation of particles from the edge part of the substrate. Silicon ions are implanted into the edge part of an SOI substrate (10) in the direction of radiuses of the SOI substrate (10) to bring a buried oxide film (2) in the edge part of the SOI substrate (10) into a silicon-rich state. Thus an SOI substrate (100) is provided, where the buried oxide film (2) has substantially been eliminated in the edge part.

公开(公告)号：US20050184342A1

公开(公告)日：2005-08-25

申请号：US11108843

申请日：2005-04-19

申请人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

发明人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

IPC分类号： H01L21/762 ,  H01L21/3205 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/52 ,  H01L27/04 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L21/336 ,  H01L21/00 ,  H01L21/331 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

摘要翻译： 在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。 电源线（21）形成在隔离绝缘膜（5）的上方。 在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。 换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面 ）。 利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。

公开(公告)号：US20050156242A1

公开(公告)日：2005-07-21

申请号：US11034938

申请日：2005-01-14

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

公开(公告)号：US06596615B2

公开(公告)日：2003-07-22

申请号：US09481385

申请日：2000-01-12

申请人： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yasuo Yamaguchi

发明人： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yasuo Yamaguchi

IPC分类号： H01L218238

CPC分类号： H01L29/66772 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/0638 ,  H01L29/78609

摘要： A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.

公开(公告)号：US06465292B2

公开(公告)日：2002-10-15

申请号：US10061211

申请日：2002-02-04

申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

IPC分类号： H01L218234

CPC分类号： H01L29/78696 ,  H01L21/76297 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/404 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78612 ,  H01L2924/0002 ,  H01L2924/00

摘要： An SOI layer is formed on a silicon substrate with a buried insulating layer therebetween. An SOI-MOSFET is formed including a drain region and a source region that are formed to define a channel formation region at the SOI layer and including a gate electrode layer opposite to the channel formation region with an insulating layer therebetween. An FS isolation structure is formed to have an FS plate opposite to a region of the SOI layer in the vicinity of the edge portion of the drain region and the source region, and to electrically isolate the SOI-MOSFET from other elements by applying a prescribed potential to the FS plate to fix the potential of the region of the SOI layer opposite to the FS plate. The channel formation region includes two edge portions on both sides and a central portion between the edge portions in a direction of a channel width, and a channel length at the edge of a prescribed region is smaller than a channel length at the central portion.

摘要翻译： 在硅衬底上形成SOI层，其间具有掩埋绝缘层。 形成SOI-MOSFET，其包括形成为在SOI层处限定沟道形成区域的漏极区域和源极区域，并且包括与沟道形成区域相对的栅极电极层，其间具有绝缘层。 FS隔离结构被形成为具有与漏极区域和源极区域的边缘部分附近的SOI层的区域相对的FS板，并且通过施加规定的方式将SOI-MOSFET与其它元件电隔离 将FS板的电位固定在与FS板相对的SOI层的区域的电位上。 通道形成区域包括两侧的两个边缘部分和沿通道宽度方向的边缘部分之间的中心部分，并且在规定区域的边缘处的通道长度小于中心部分处的通道长度。

公开(公告)号：US06424010B1

公开(公告)日：2002-07-23

申请号：US09169903

申请日：1998-10-09

申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

IPC分类号： H01L2976

摘要： An SOI layer is formed on a silicon substrate with a buried insulating layer therebetween. An SOI-MOSFET is formed including a drain region and a source region that are formed to define a channel formation region at the SOI layer and including a gate electrode layer opposite to the channel formation region with an insulating layer therebetween. A field-shield (FS) isolation structure is formed to have an FS plate opposite to a region of the SOI layer in the vicinity of the edge portion of the drain region and the source region, and to electrically isolate the SOI-MOSFET from other elements by applying a prescribed potential to the FS plate to fix the potential of the region of the SOI layer opposite to the FS plate. The channel formation region includes the edge portions on both sides and a central portion between the edge portions in a direction of a channel width, and a channel length at the edge of prescribed region is smaller than a channel length at the central portion.

公开(公告)号：US06232201B1

公开(公告)日：2001-05-15

申请号：US09113155

申请日：1998-07-10

申请人： Yoshiko Yoshida ,  Hideki Naruoka ,  Yasuhiro Kimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

发明人： Yoshiko Yoshida ,  Hideki Naruoka ,  Yasuhiro Kimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

IPC分类号： H01L2176

CPC分类号： H01L21/7624 ,  H01L21/3105 ,  H01L21/31155

摘要： An object is to provide a semiconductor substrate processing method and a semiconductor substrate that prevent formation of particles from the edge part of the substrate. Silicon ions are implanted into the edge part of an SOI substrate (10) in the direction of radiuses of the SOI substrate (10) to bring a buried oxide film (2) in the edge part of the SOI substrate (10) into a silicon-rich state. Thus an SOI substrate (100) is provided, where the buried oxide film (2) has substantially been eliminated in the edge part.

摘要翻译： 目的在于提供一种半导体衬底处理方法以及防止从衬底的边缘部分形成微粒的半导体衬底。 在SOI衬底（10）的半径方向上将硅离子注入到SOI衬底（10）的边缘部分中，以使SOI衬底（10）的边缘部分中的掩埋氧化膜（2）成为硅 丰富的状态。 因此，提供SOI衬底（100），其中掩埋氧化膜（2）在边缘部分中基本上被去除。