公开(公告)号：US20060073682A1

公开(公告)日：2006-04-06

申请号：US10711764

申请日：2004-10-04

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： H01L21/28

CPC分类号： H01L21/02115 ,  B82Y10/00 ,  H01L21/02282 ,  H01L21/3146 ,  H01L21/3185 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76888 ,  H01L2221/1047

摘要： A low-k dielectric material for use in the manufacture of semiconductor devices, semiconductor structures using the low-k dielectric material, and methods of forming such dielectric materials and fabricating such structures. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic state. The carbon nanostructures may be converted to the insulating electronic state either before or after a layer containing the carbon nanostructures is formed on a substrate. One approach for converting the carbon nanostructures to the insulating electronic state is fluorination.

摘要翻译： 用于制造半导体器件的低k电介质材料，使用低k电介质材料的半导体结构，以及形成这种介电材料和制造这种结构的方法。 低k介电材料包括碳纳米结构，如碳纳米管或碳​​棒球，其特征在于绝缘电子状态。 碳纳米结构可以在包含碳纳米结构的层在基底上形成之前或之后转变为绝缘电子状态。 将碳纳米结构转化为绝缘电子态的一种方法是氟化。

公开(公告)号：US20060073394A1

公开(公告)日：2006-04-06

申请号：US10711758

申请日：2004-10-04

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： G03C5/00 ,  G06F17/50 ,  G03F1/00

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338

摘要： A combined wide-image and loop-cutter pattern is provided for both cutting and forming a wide-image section to a hard mask on a substrate formed by sidewall imaging techniques in a reduced number of photolithographic steps. A single mask is formed which provides a wide mask section while additionally providing a mask to protect the critical edges of an underlying hard mask during hard mask etching. After the hard mask is cut into sections, the protective portions of the follow-on mask are removed to expose the critical edges of the underlying hard mask while maintaining shapes necessary for defining wide-image sections. Thus, the hard mask cutting, hard mask critical edge protecting, and large area mask may be formed in a reduced number of steps.

摘要翻译： 提供了组合的宽图像和环形切割器图案，用于在通过减少数量的光刻步骤的侧壁成像技术形成的基板上切割和形成宽图像部分到硬掩模。 形成单个掩模，其提供宽掩模部分，同时另外提供掩模以在硬掩模蚀刻期间保护下面的硬掩模的临界边缘。 在将硬掩模切割成部分之后，除去后续掩模的保护部分以暴露下面的硬掩模的临界边缘，​​同时保持限定宽图像部分所需的形状。 因此，可以以减少的步数形成硬掩模切割，硬掩模临界边缘保护和大面积掩模。

公开(公告)号：US20050245008A1

公开(公告)日：2005-11-03

申请号：US10709314

申请日：2004-04-28

申请人： Bruce Doris ,  Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Bruce Doris ,  Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/28 ,  H01L21/31 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/44 ,  H01L21/469 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/49

CPC分类号： H01L21/823437 ,  H01L21/28097 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/4975

摘要： A method for forming a gate structure for a semiconductor device includes defining a conductive sacrificial structure on a substrate, forming a reacted metal film on sidewalls of the conductive sacrificial structure, and removing unreacted portions of the conductive sacrificial structure.

摘要翻译： 用于形成半导体器件的栅极结构的方法包括在衬底上限定导电牺牲结构，在导电牺牲结构的侧壁上形成反应的金属膜，以及去除导电牺牲结构的未反应部分。

公开(公告)号：US20050242378A1

公开(公告)日：2005-11-03

申请号：US11175582

申请日：2005-07-06

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/338 ,  H01L29/49 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L29/66772 ,  H01L21/2807 ,  H01L29/4908

摘要： A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

摘要翻译： 一种制造金属氧化物半导体器件结构的方法。 该方法包括通过离子注入将掺杂剂物质同时引入覆盖在半导体有源层上的绝缘层和栅电极的半导体有源层中。 选择半导体有源层的厚度，栅电极的厚度和掺杂剂物质的动能，使得半导体有源层和绝缘层中的掺杂剂物质的投影范围位于绝缘层内，并且投影 栅电极中的掺杂物种类的范围位于栅电极内。 结果，半导体有源层和栅电极可以在单个离子注入期间同时掺杂，而不需要另外的注入掩模。

公开(公告)号：US20070262450A1

公开(公告)日：2007-11-15

申请号：US11379582

申请日：2006-04-21

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： H01L23/52

CPC分类号： H01L23/53276 ,  H01L23/5256 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

摘要： A fuse structure and a method for operating the same. The fuse structure operating method includes providing a structure. The structure includes (a) an electrically conductive layer and (b) N electrically conductive regions hanging over without touching the electrically conductive layer. N is a positive integer and N is greater than 1. The N electrically conductive regions are electrically connected together. The structure operating method further includes causing a first electrically conductive region of the N electrically conductive regions to touch the electrically conductive layer without causing the remaining N−1 electrically conductive regions to touch the electrically conductive layer.

摘要翻译： 熔丝结构及其操作方法。 熔丝结构操作方法包括提供一种结构。 该结构包括（a）导电层和（b）悬挂在不接触导电层的N个导电区域。 N是正整数，N大于1.N导电区域电连接在一起。 结构操作方法还包括使N个导电区域的第一导电区域与导电层接触而不会使剩余的N-1导电区域接触导电层。

公开(公告)号：US20070190713A1

公开(公告)日：2007-08-16

申请号：US11307671

申请日：2006-02-16

申请人： Bruce Doris ,  Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Bruce Doris ,  Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： H01L21/8238

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/823828 ,  H01L21/823864

摘要： A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial polymer containing silicon that is deposited over a gate conductor layer and covered by a cover layer. The sacrificial polymer layer is patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the polymer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.

摘要翻译： 用于形成亚光刻结构的侧壁图像转印工艺使用沉积在栅极导体层上并被覆盖层覆盖的含有硅的牺牲聚合物层。 牺牲聚合物层用常规抗蚀剂图案化并蚀刻以形成牺牲心轴。 心轴的边缘在低温下在等离子体中被氧化或氮化，之后剥离聚合物和覆盖层，留下亚光刻的侧壁。 侧壁用作硬掩模来蚀刻栅极导体层中的亚光刻栅极结构。

公开(公告)号：US20070166981A1

公开(公告)日：2007-07-19

申请号：US11335372

申请日：2006-01-19

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam

IPC分类号： H01L21/44

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76885

摘要： Methods for fabricating a semiconductor device include forming a first layer on an underlying layer, forming a hardmask on the first layer, and patterning holes through the hardmask and first layer. An overhang is formed extending over sides of the holes. A conformal layer is deposited over the overhang and in the holes until the conformal layer closes off the holes to form a void/seam in each hole. The void/seam in each hole is exposed by etching back a top surface. The void/seam in each hole is extended to the underlying layer.

摘要翻译： 制造半导体器件的方法包括在下层上形成第一层，在第一层上形成硬掩模，以及通过硬掩模和第一层图形化孔。 形成在孔的侧面上延伸的突出端。 保形层沉积在悬垂孔和孔中，直到共形层封闭孔，以在每个孔中形成空隙/接缝。 每个孔中的空隙/接缝通过蚀刻顶部表面而暴露出来。 每个孔中的空隙/接缝延伸到下层。

公开(公告)号：US20070125946A1

公开(公告)日：2007-06-07

申请号：US11164792

申请日：2005-12-06

申请人： Carol Boye ,  Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Carol Boye ,  Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： G21K7/00

CPC分类号： G01Q60/42 ,  G01Q70/12

摘要： A Y-shaped carbon nanotube atomic force microscope probe tip and methods comprise a shaft portion; a pair of angled arms extending from a same end of the shaft portion, wherein the shaft portion and the pair of angled arms comprise a chemically modified carbon nanotube, and wherein the chemically modified carbon nanotube is modified with any of an amine, carboxyl, fluorine, and metallic component. Preferably, each of the pair of angled arms comprises a length of at least 200 nm and a diameter between 10 and 200 nm. Moreover, the chemically modified carbon nanotube is preferably adapted to allow differentiation between substrate materials to be probed. Additionally, the chemically modified carbon nanotube is preferably adapted to allow fluorine gas to flow through the chemically modified carbon nanotube onto a substrate to be characterized. Furthermore, the chemically modified carbon nanotube is preferably adapted to chemically react with a substrate surface to be characterized.

摘要翻译： Y型碳纳米管原子力显微镜探针头和方法包括轴部分; 一对成角度的臂，其从所述轴部的同一端延伸，其中所述轴部和所述一对成角度的臂包括化学改性的碳纳米管，并且其中所述化学改性的碳纳米管用胺，羧基，氟 ，和金属成分。 优选地，一对成角度的臂中的每一个包括至少200nm的长度和10和200nm之间的直径。 此外，化学改性的碳纳米管优选适于允许待探测的基底材料之间的分化。 此外，化学改性的碳纳米管优选适于使氟气通过化学改性的碳纳米管流动到待表征的基底上。 此外，化学改性的碳纳米管优选适于与要表征的基材表面发生化学反应。

公开(公告)号：US20070023839A1

公开(公告)日：2007-02-01

申请号：US11161219

申请日：2005-07-27

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L29/4908 ,  H01L29/66795 ,  H01L51/0048 ,  H01L51/0512

摘要： A fin field effect transistor (FinFET) gate comprises a semiconductor wafer; a gate dielectric layer over the semiconductor wafer; a conductive material on the gate dielectric layer; an activated carbon nanotube on a surface of the conductive material; and a plated metal layer on the activated carbon nanotube. Preferably, the carbon nanotube is on a sidewall of the conductive material. The conductive material comprises a first metal layer over the gate dielectric layer, wherein the first metal layer acts as a catalyst for growing the carbon nanotube, wherein the first metal layer is preferably in a range of 1-10 nm in thickness. The semiconductor wafer may comprise a silicon on insulator wafer. The FinFET gate may further comprise a second metal layer disposed between the first metal layer and the gate dielectric layer.

摘要翻译： 鳍状场效应晶体管（FinFET）栅极包括半导体晶片; 半导体晶片上的栅介质层; 栅介电层上的导电材料; 导电材料表面上的活性炭纳米管; 和活化碳纳米管上的电镀金属层。 优选地，碳纳米管位于导电材料的侧壁上。 导电材料包括在栅极介电层上的第一金属层，其中第一金属层用作生长碳纳米管的催化剂，其中第一金属层的厚度优选在1-10nm的范围内。 半导体晶片可以包括绝缘体上硅晶片。 FinFET栅极还可以包括设置在第一金属层和栅极介电层之间的第二金属层。

公开(公告)号：US20050098804A1

公开(公告)日：2005-05-12

申请号：US10703355

申请日：2003-11-07

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/338 ,  H01L29/49 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L29/66772 ,  H01L21/2807 ,  H01L29/4908

摘要： A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.