公开(公告)号：US4216638A

公开(公告)日：1980-08-12

申请号：US895226

申请日：1978-04-10

Applicant: Toshio Yoshida

Inventor： Toshio Yoshida

IPC: B29C65/00 ,  B29C65/18 ,  B29C65/22 ,  B29C65/30 ,  B65B9/06 ,  B65B51/18

CPC classification number: B65B51/18 ,  B29C65/18 ,  B29C65/224 ,  B29C65/228 ,  B29C65/229 ,  B29C65/30 ,  B29C66/1122 ,  B29C66/431 ,  B29C66/4312 ,  B29C66/4322 ,  B29C66/81821 ,  B29C66/81871 ,  B29C66/83413 ,  B29C66/83423 ,  B29C66/83513 ,  B29C66/91411 ,  B29C66/91443 ,  B29C66/91655 ,  B29C66/91931 ,  B29C66/91951

Abstract: A wrapping machine has a heat sealing band running horizontally forward along a feed passage which lies in front of a former which forms a strip piece of film into a tube. The heat sealing band is put on a pair of electrode pulleys, and its upper portion between a pair of the electrode pulleys which runs along the feed passage is charged with electricity directly through a pair of the electrode pulleys.

Abstract translation: 包装机具有沿着位于前者前方的进料通道水平向前延伸的热封带，其将薄膜条形成管。 热封带放在一对电极皮带轮上，其一部分沿馈电通道延伸的一对电极皮带轮之间的上部通过一对电极皮带轮直接充电。

公开(公告)号：US4058883A

公开(公告)日：1977-11-22

申请号：US651282

申请日：1976-01-22

Applicant: Toshio Yoshida ,  Kiyoshi Terai ,  Shigetomo Matsui ,  Tsuneo Kinoshita ,  Akira Hoshi ,  Toru Tohmoto

Inventor： Toshio Yoshida ,  Kiyoshi Terai ,  Shigetomo Matsui ,  Tsuneo Kinoshita ,  Akira Hoshi ,  Toru Tohmoto

IPC: B61D17/04 ,  B61D17/12 ,  B23P11/02 ,  B23K28/02

CPC classification number: B61D17/12 ,  B61D17/043 ,  Y10T29/49867

Abstract: A panel structure is fabricated by stretching a skin plate with a tensile stress below the elastic limit stress thereof, securing this plate onto a framework with the plate under a constraining tensile stress and with portions thereof to which the constraining stress is not being fully applied being heated thereby to cause thermal expansion thereof, removing the constraining stress, and permitting the plate to cool and thereby to undergo thermal contraction and deformation, thereby producing tensile residual stress within the plate, whereby occurrence of welding deformations in the plate on the finished panel is prevented. Depending on the necessity, the skin plate may be prestretched with a stress exceeding the yield point thereof before the above described panel fabrication.

Abstract translation: 通过将拉伸应力拉伸到低于其弹性极限应力的拉伸应力下来制造面板结构，将该板固定在具有约束拉伸应力的板的框架上，并且其中约束应力未被完全施加到其上的部分 加热从而引起其热膨胀，消除约束应力，并允许板冷却，从而发生热收缩和变形，由此在板内产生拉伸残余应力，从而在成品板上的板中发生焊接变形 防止了 根据需要，在上述面板制造之前，可以将表皮板预拉伸超过其屈服点的应力。

公开(公告)号：US08561079B2

公开(公告)日：2013-10-15

申请号：US12635801

申请日：2009-12-11

Applicant: Takashi Suzuki ,  Toshio Yoshida

Inventor： Takashi Suzuki ,  Toshio Yoshida

IPC: G06F9/46 ,  G06F15/00

CPC classification number: G06F9/3851

Abstract: The information processing device in the simultaneous multi-threading system is operated in an inter-thread performance load arbitration control method, and includes: an instruction input control unit for sharing among threads control of inputting an instruction in an arithmetic unit for acquiring the instruction from memory and performing an operation on the basis of the instruction; a commit stack entry provided for each thread for holding information obtained by decoding the instruction; an instruction completion order control unit for updating the memory and a general purpose register depending on an arithmetic result obtained by the arithmetic unit in an order of the instructions input from the instruction input control unit; and a performance load balance analysis unit for detecting the information registered in the commit stack entry and controlling the instruction input control unit.

Abstract translation: 同时多线程系统中的信息处理装置以线程间性能负载仲裁控制方式进行操作，包括：指令输入控制单元，用于在线程之间共享输入用于获取指令的算术单元中的指令的控制 存储器并基于该指令执行操作; 为每个线程提供的用于保存通过解码指令而获得的信息的提交栈条目; 指令完成顺序控制单元，用于根据从指令输入控制单元输入的指令的顺序，根据运算单元获得的运算结果来更新存储器和通用寄存器; 以及性能负载平衡分析单元，用于检测在提交堆栈条目中登记的信息并控制指令输入控制单元。

公开(公告)号：US08407714B2

公开(公告)日：2013-03-26

申请号：US12638760

申请日：2009-12-15

Applicant: Norihito Gomyo ,  Toshio Yoshida ,  Ryuichi Sunayama

Inventor： Norihito Gomyo ,  Toshio Yoshida ,  Ryuichi Sunayama

IPC: G06F9/46 ,  G06F9/44 ,  G06F15/76 ,  G06F11/00

CPC classification number: G06F9/3851 ,  G06F9/30083 ,  G06F9/3009 ,  G06F9/30189 ,  G06F9/3885

Abstract: An arithmetic device simultaneously processes a plurality of threads and may continue the process by minimizing the degradation of the entire performance although a hardware error occurs. An arithmetic device 100 includes: an instruction execution circuit 101 capable of selectively executing a mode in which the instruction sequences of a plurality of threads are executed and a mode in which the instruction sequence of a single thread is executed; and a switch indication circuit 102 instructing the instruction execution circuit 101 to switch a thread mode.

Abstract translation: 算术装置同时处理多个线程，并且可以通过尽可能降低整个性能的劣化来继续该过程，尽管发生硬件错误。 算术装置100包括：指令执行电路101，其能够选择性地执行执行多个线程的指令序列的模式以及执行单线程的指令序列的模式; 和指示执行电路101切换线程模式的开关指示电路102。

公开(公告)号：US07984271B2

公开(公告)日：2011-07-19

申请号：US11875431

申请日：2007-10-19

Applicant: Mariko Sakamoto ,  Toshio Yoshida

Inventor： Mariko Sakamoto ,  Toshio Yoshida

IPC: G06F9/30

CPC classification number: G06F9/3867 ,  G06F9/30181 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

Abstract: A processor device having a reservation station (RS) is concerned. In case the processor device has plural RS, the RS is associated with an arithmetic pipeline, and two RS make a pair. When one RS of the pair cannot dispatch an instruction to an associated arithmetic pipeline, the other RS dispatches the instruction to that arithmetic pipeline, or delivers its held instruction to the one RS. In case one RS is equipped, plural entries in the RS are divided into groups, and by dynamically changing this grouping according to the dispatch frequency of the instruction to the arithmetic pipelines or the held state of the instructions, the arithmetic pipelines are efficiently utilized. Incidentally, depending on the grouping of the plural entries in the RS, a configuration as if the plural RS were allocated to each arithmetic pipeline may be realized.

Abstract translation: 涉及具有保留站（RS）的处理器设备。 在处理器设备具有多个RS的情况下，RS与算术流水线相关联，并且两个RS成对。 当该对的一个RS不能向相关联的算术流水线发送指令时，另一个RS将指令发送到该算术流水线，或者将其保持的指令递送到一个RS。 在配备一个RS的情况下，RS中的多个条目被分成组，并且通过根据指令的调度频率动态地改变该分组到算术流水线或指令的保持状态，可以有效地利用算术流水线。 顺便提及，根据RS中的多个条目的分组，可以实现如同将多个RS分配给每个运算管线的配置。

公开(公告)号：US07945766B2

公开(公告)日：2011-05-17

申请号：US12323044

申请日：2008-11-25

Applicant: Toshio Yoshida

Inventor： Toshio Yoshida

IPC: G06F9/312

CPC classification number: G06F9/3001 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3887

Abstract: A processor capable of executing conditional store instructions without being limited by the number of condition codes is provided. Condition data is stored in floating-point registers, and an operation unit executes a conditional floating-point store instruction of determining whether to store, in cache, store data.

Abstract translation: 提供了能够执行条件存储指令而不受条件码数量限制的处理器。 条件数据存储在浮点寄存器中，操作单元执行条件浮点存储指令，该指令确定是否在高速缓存中存储存储数据。

公开(公告)号：US20110035572A1

公开(公告)日：2011-02-10

申请号：US12805476

申请日：2010-08-02

Applicant: Yasunobu Akizuki ,  Toshio Yoshida

Inventor： Yasunobu Akizuki ,  Toshio Yoshida

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891

Abstract: Multiple data processing instructions instruct a computing device to process multiple data including first data and second data. When a multiple data processing instruction is decoded, two allocatable registers are selected. One is used to store the result of a processing operation performed on first data by one processing unit, and the other is used to store the result of a processing operation performed on second data by another processing unit. Those stored processing results are then transferred to result registers. Normal data processing instructions, on the other hand, instruct a processing operation on third data. When a normal data processing instruction is decoded, one allocatable register is selected and used to store the result of processing that a processing unit performs on the third data. The stored processing result is then transferred to a result register.

Abstract translation: 多个数据处理指令指示计算设备处理包括第一数据和第二数据的多个数据。 当多重数据处理指令被解码时，选择两个可分配寄存器。 一个用于存储由一个处理单元对第一数据执行的处理操作的结果，另一个用于存储由另一处理单元对第二数据执行的处理操作的结果。 然后将那些存储的处理结果传送到结果寄存器。 另一方面，正常数据处理指令指示关于第三数据的处理操作。 当正常数据处理指令被解码时，选择一个可分配寄存器并用于存储处理单元对第三数据执行的处理结果。 然后将存储的处理结果传送到结果寄存器。

公开(公告)号：US20110021394A1

公开(公告)日：2011-01-27

申请号：US12933805

申请日：2009-03-12

Applicant: Hajime Nakao ,  Shozaburo Konishi ,  Toshio Yoshida

Inventor： Hajime Nakao ,  Shozaburo Konishi ,  Toshio Yoshida

IPC: C10M169/04

CPC classification number: C10M137/04 ,  C10M137/08 ,  C10M141/10 ,  C10M169/04 ,  C10M2203/1025 ,  C10M2215/04 ,  C10M2223/04 ,  C10M2223/043 ,  C10N2220/025 ,  C10N2230/02 ,  C10N2230/43 ,  C10N2240/40

Abstract: A lubricating oil composition comprising a lubricating base oil, and a mixture and/or a reaction product of (A) 0.01-0.5% by mass of at least one compound selected from among acid phosphates represented by formula (1) or formula (2), and (B) 0.01-2% by mass of an alkylamine represented by formula (3), based on the total weight of the composition, wherein the acid value due to component (A) is 0.1-1.0 mgKOH/g. [R1 and R2 represent hydrogen or straight-chain alkyl or straight-chain alkenyl groups, with at least one of R1 and R2 being a C6-12 straight-chain alkyl or straight-chain alkenyl group; R3 and R4 represent hydrogen straight-chain alkyl or straight-chain alkenyl groups, with at least one of R3 and R4 being a C13-18 straight-chain alkyl or straight-chain alkenyl group; and R5 and R6 represent hydrogen or C4-30 branched-chain alkyl groups, with at least one of R5 and R6 being a branched-chain alkyl group.]

Abstract translation: 一种润滑油组合物，其含有（A）0.01-0.5质量％的至少一种选自式（1）或式（2）表示的酸式磷酸酯的化合物的混合物和/或反应产物， ，（B）0.01-2质量％的由式（3）表示的烷基胺，基于组合物的总重量，其中由组分（A）引起的酸值为0.1-1.0mgKOH / g。 [R 1和R 2表示氢或直链烷基或直链烯基，其中R 1和R 2中的至少一个是C 6-12直链烷基或直链烯基; R3和R4代表氢直链烷基或直链烯基，其中R3和R4中的至少一个是C13-18直链烷基或直链烯基; 并且R 5和R 6表示氢或C 4-30支链烷基，其中R 5和R 6中的至少一个是支链烷基。

公开(公告)号：US20100332802A1

公开(公告)日：2010-12-30

申请号：US12801868

申请日：2010-06-29

Applicant: Atsushi Fusejima ,  Yasunobu Akizuki ,  Toshio Yoshida

Inventor： Atsushi Fusejima ,  Yasunobu Akizuki ,  Toshio Yoshida

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/3001 ,  G06F9/3885 ,  G06F9/3891

Abstract: A priority circuit is connected to a reservation station and a plurality of arithmetic units that processes different operations and dispatches, when it is determined that an executable flag indicating that an instruction can be executed by only a specific arithmetic unit is on, an instruction to an arithmetic unit that is different from the specific arithmetic unit and of which a queue is vacant in accordance with the input performed by an instruction decoder and the reservation station.

Abstract translation: 优先电路连接到保留站和处理不同的操作和调度的多个算术单元，当确定指示只能由特定算术单元执行指令的可执行标志被打开时，指令 算术单元，其与特定运算单元不同，并且根据由指令解码器和保留站执行的输入，其队列空闲。

公开(公告)号：US20100325396A1

公开(公告)日：2010-12-23

申请号：US12805630

申请日：2010-08-10

Applicant: Toshio Yoshida

Inventor： Toshio Yoshida

IPC: G06F9/302

CPC classification number: G06F9/3851 ,  G06F9/30127

Abstract: The present invention relates to a multithread processor, and this multithread processor comprises a plurality of register windows each provided for each of threads and capable of storing data to be used for instruction processing in an arithmetic unit, a work register capable of mutually transferring data with respect to the plurality of register windows and the arithmetic unit and a multithread control unit for controlling data transfer among the plurality of register windows, the work register and the arithmetic unit on the basis of an execution thread identifier for identifying the thread to be executed in the arithmetic unit. This enables conducting the multithread processing at a high speed.