摘要:
A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.
摘要:
A method of forming a semiconductor structure includes providing a semiconductor substrate and forming a memory cell at a surface of the semiconductor substrate. The step of forming the memory cell includes forming a gate dielectric on the semiconductor substrate and a control gate on the gate dielectric; forming a first and a second tunneling layer on a source side and a drain side of the memory cell, respectively; tilt implanting a lightly doped source region underlying the first tunneling layer, wherein the tilt implanting tilts only from the source side to the drain side, and wherein a portion of the semiconductor substrate under the second tunneling layer is free from the tilt implanting; forming a storage on a horizontal portion of the second tunneling layer; and forming a source region and a drain region in the semiconductor substrate.
摘要:
An array includes a transistor cpmprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.
摘要:
A method for constructing a phase change memory device includes forming a first dielectric layer on a substrate; forming a first conductive component in the first dielectric layer; forming a second dielectric layer over the first conductive component in the first dielectric layer; forming a conductive crown in the second dielectric layer, the conductive crown being in contact and alignment with the conductive component; depositing a third dielectric layer in the conductive crown; and forming a trench filled with chalcogenic materials having an amorphous phase and a crystalline phase programmable by controlling a temperature thereof to represent logic states, wherein the trench extends across the conductive crown, such that the trench is free from a rounded end portion caused by lithography during fabrication of the phase change memory device.
摘要:
A method for constructing a phase change memory device includes forming a first dielectric layer on a substrate; forming a first conductive component in the first dielectric layer; forming a second dielectric layer over the first conductive component in the first dielectric layer; forming a conductive crown in the second dielectric layer, the conductive crown being in contact and alignment with the conductive component; depositing a third dielectric layer in the conductive crown; and forming a trench filled with chalcogenic materials having an amorphous phase and a crystalline phase programmable by controlling a temperature thereof to represent logic states, wherein the trench extends across the conductive crown, such that the trench is free from a rounded end portion caused by lithography during fabrication of the phase change memory device.
摘要:
A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.
摘要:
A system and method for a sidewall SONOS memory device is provided. An electronic device includes a non-volatile memory. A substrate includes source/drain regions. A gate stack is directly over the substrate and between the source/drain regions. The gate stack has a sidewall. A nitride spacer is formed adjacent to the gate stack. A first oxide material is formed directly adjacent the spacer. An oxide-nitride-oxide structure is formed between the spacer and the gate stack. The oxide-nitride-oxide structure has a generally L-shaped cross-section on at least one side of the gate stack. The oxide-nitride-oxide structure includes a vertical portion and a horizontal portion. The vertical portion is substantially aligned with the sidewall and located between the first oxide material and the gate sidewall. The horizontal portion is substantially aligned with the substrate and located between the first oxide and the substrate.
摘要:
A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material.
摘要:
An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.
摘要:
An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.