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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    21.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20180033961A1

    公开(公告)日：2018-02-01

    申请号：US15260754

    申请日：2016-09-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Liang Yi ,  Chia-Ching Hsu ,  Shen-De Wang ,  Ko-Chi Chen

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a bottom metal layer, a resistive random access memory (ReRAM) cell structure, and an upper metal layer. The bottom metal layer is located above the substrate. The ReRAM cell structure is formed on the bottom metal layer. The ReRAM cell structure includes a bottom electrode, a memory cell layer, a top electrode, and a spacer. The memory cell layer is formed on the bottom electrode. The top electrode is formed on the memory cell layer. The spacer is formed on two sides of the bottom electrode, the memory cell layer and the top electrode. The upper metal layer is electrically connected to and directly contacting the top electrode.

    Split gate non-volatile memory device and method for fabricating the same
    24.
    发明授权
    Split gate non-volatile memory device and method for fabricating the same 有权
    分闸非易失性存储器件及其制造方法

    公开(公告)号：US09379128B1

    公开(公告)日：2016-06-28

    申请号：US14809342

    申请日：2015-07-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Liang Yi ,  Ko-Chi Chen ,  Shen-De Wang ,  Chia-Ching Hsu ,  Chun-Sung Huang ,  Wen-Peng Hsu

    IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28 ,  H01L21/225

    CPC classification number: H01L27/11568 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

    Abstract: A split gate NVM device includes a semiconductor substrate, an ONO structure disposed on the semiconductor substrate, a first gate electrode disposed on the ONO structure, a second gate electrode disposed on the semiconductor substrate, adjacent to and insulated from the first gate electrode and the ONO structure, a first doping region with a first conductivity formed in the semiconductor substrate and adjacent to the ONO structure, a second doping region with the first conductivity formed in the semiconductor substrate and adjacent to the second gate electrode, and a third doping region with the first conductivity formed in the semiconductor substrate, disposed between the first doping region and the second doping region and adjacent to the ONO structure and the second gate electrode.

    Abstract translation: 分路门NVM器件包括半导体衬底，设置在半导体衬底上的ONO结构，设置在ONO结构上的第一栅电极，设置在半导体衬底上的第二栅极，与第一栅电极相邻并绝缘， ONO结构，在半导体衬底中形成并与ONO结构相邻的具有第一导电性的第一掺杂区，在半导体衬底中形成并与第二栅电极相邻的具有第一导电性的第二掺杂区，以及第三掺杂区， 所述第一导电体形成在所述半导体衬底中，设置在所述第一掺杂区域和所述第二掺杂区域之间并且邻近所述ONO结构和所述第二栅电极。

    SEMICONDUCTOR MEMORY DEVICE
    25.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20240397838A1

    公开(公告)日：2024-11-28

    申请号：US18795158

    申请日：2024-08-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Ching Hsu

    IPC: H10N70/00 ,  H10N70/20

    Abstract: A semiconductor memory device includes a substrate; a first dielectric layer on the substrate; and bottom electrodes on the first dielectric layer. The bottom electrodes are arranged equidistantly in a first direction and extend along a second direction. A second dielectric layer is disposed on the first dielectric layer. Top electrodes are disposed in the second dielectric layer and arranged at intervals along the second direction. Each top electrode includes a lower portion located around each bottom electrode and a tapered upper portion. A third dielectric layer is disposed above the bottom electrodes and around the tapered upper portion. A resistive-switching layer is disposed between a sidewall of each bottom electrode and a sidewall of the lower portion and between the third dielectric layer and a sidewall of the tapered upper portion. An air gap is disposed in the third dielectric layer.

    Method for forming resistive random-access memory device
    26.
    发明授权
    Method for forming resistive random-access memory device 有权

    公开(公告)号：US12156487B2

    公开(公告)日：2024-11-26

    申请号：US18382055

    申请日：2023-10-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

    IPC: H10N70/00 ,  H10B63/00

    Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.

    METHOD FOR FORMING A SEMICONDUCTOR MEMORY DEVICE
    27.
    发明公开
    METHOD FOR FORMING A SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240260489A1

    公开(公告)日：2024-08-01

    申请号：US18635027

    申请日：2024-04-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Ching Hsu

    IPC: H10N70/00 ,  H10N70/20

    CPC classification number: H10N70/8265 ,  H10N70/021 ,  H10N70/245 ,  H10N70/841 ,  H10N70/8833

    Abstract: A semiconductor memory device includes a substrate, a first dielectric layer on the substrate, a bottom electrode on the first dielectric layer, a second dielectric layer on the first dielectric layer, and a top electrode in the second dielectric layer. The top electrode has a lower portion around the bottom electrode and a tapered upper portion. A third dielectric layer is disposed above the bottom electrode and around the tapered upper portion of the top electrode. A resistive-switching layer is disposed between a sidewall of the bottom electrode and a sidewall of the lower portion of the top electrode and between the third dielectric layer and a sidewall of the tapered upper portion of the top electrode. An air gap is disposed in the third dielectric layer.

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