公开(公告)号：US10475648B1

公开(公告)日：2019-11-12

申请号：US15968680

申请日：2018-05-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ming-Te Wei ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Chien-Ting Ho

IPC: H01L21/033 ,  H01L21/02 ,  H01L27/108 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311

Abstract: A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.

公开(公告)号：US10431587B2

公开(公告)日：2019-10-01

申请号：US15859756

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Tsen Liu ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: H01L27/108 ,  H01L29/08 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311

Abstract: A semiconductor device and a manufacturing method thereof are provided. The method includes providing a substrate, a plurality of word lines and a plurality of bit lines, and then forming a storage node contact on each source/drain region, so that a width of a top surface of each storage node contact in a direction is less than a width of a bottom surface of each storage node contact.

公开(公告)号：US10361209B2

公开(公告)日：2019-07-23

申请号：US16043166

申请日：2018-07-24

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho ,  Wen-Chieh Lu ,  Li-Wei Liu

IPC: H01L27/108

Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.

公开(公告)号：US10249510B1

公开(公告)日：2019-04-02

申请号：US15908733

申请日：2018-02-28

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Yu-Chieh Lin ,  Tsung-Ying Tsai ,  Chien-Ting Ho

IPC: H01L21/02 ,  H01L21/311 ,  H01L27/105 ,  H01L21/768 ,  H01L21/308

Abstract: An etching method including the following steps is provided. A substrate is provided first. A first region and a second region adjacent to the first region are defined on the substrate. A material layer is formed on the substrate. A pattern mask is formed on the material layer. The patterned mask includes a first part covering the material layer on the first region and a second part including a lattice structure. The lattice structure includes a plurality of openings and a plurality of shielding parts. Each opening exposes a part of the material layer on the second region. Each shielding part is located between the openings adjacent to one another. Each shielding part covers a part of the material layer on the second region. An isotropic etching process is then performed to remove the material layer exposed by the openings and the material layer covered by the shielding parts.

公开(公告)号：US10204914B2

公开(公告)日：2019-02-12

申请号：US15856022

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Cheng Tsai ,  Feng-Ming Huang ,  Ying-Chiao Wang ,  Chien-Ting Ho ,  Li-Wei Feng ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first buried gate and a second buried gate in the substrate on the memory region; forming a first silicon layer on the substrate on the periphery region; forming a stacked layer on the first silicon layer; forming an epitaxial layer on the substrate between the first buried gate and the second buried gate; and forming a second silicon layer on the epitaxial layer on the memory region and the stacked layer on the periphery region.

公开(公告)号：US10181473B2

公开(公告)日：2019-01-15

申请号：US15452746

申请日：2017-03-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Tsung-Ying Tsai ,  Kai-Ping Chen ,  Chien-Ting Ho

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a substrate, plural active areas, plural bit lines and plural dummy bit lines. The substrate includes a cell region and a periphery region, and the active areas are defined on the substrate. The bit lines are disposed on the substrate, within the cell region and across the active areas. The dummy bit lines are disposed at a side of the bit lines, wherein the dummy bit lines are in contact with each other and have different pitches therebetween.

公开(公告)号：US20180294269A1

公开(公告)日：2018-10-11

申请号：US15915042

申请日：2018-03-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Chien-Ting Ho ,  Kai-Ping Chen

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768

Abstract: A semiconductor structure having a contact plug includes a substrate. A memory cell region and a peripheral circuit region are defined on the substrate. At least one memory cell is disposed on the substrate within the memory cell region. The memory cell includes a transistor and a capacitor structure. A first planar stacked dielectric layer covers the peripheral circuit region. The first planar stacked dielectric layer includes two first dielectric layers and a second dielectric layer. The first dielectric layer at the bottom of the first planar stacked dielectric layer extends to the memory cell region and covers the capacitor structure. A contact plug is disposed at the peripheral circuit region and penetrates the first planar stacked dielectric layer.

公开(公告)号：US10079277B2

公开(公告)日：2018-09-18

申请号：US15362771

申请日：2016-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tri-Rung Yew ,  Hung-Chan Lin ,  Li-Wei Feng ,  Chien-Ting Ho ,  Chia-Lung Chang

IPC: H01L21/20 ,  H01L49/02 ,  H01L21/311 ,  H01L21/3205 ,  H01L27/108

CPC classification number: H01L28/82 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32051 ,  H01L27/10852 ,  H01L28/87 ,  H01L28/91

Abstract: A method of fabricating a metal-insulator-metal capacitor includes providing a dielectric layer. The dielectric layer is etched to form a first hole including a first convex profile bulging into the dielectric layer. Subsequently, the dielectric layer is etched to form a second hole including a second convex profile bulging into the dielectric layer. A first metal layer is formed to conformally cover the capacitor trench. An insulating layer is formed to cover the first metal layer. Finally, a second metal layer is formed covering the insulating layer.

公开(公告)号：US20180261603A1

公开(公告)日：2018-09-13

申请号：US15479294

申请日：2017-04-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho ,  Wen-Chieh Lu ,  Li-Wei Liu

IPC: H01L27/108

Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.

公开(公告)号：US10074656B1

公开(公告)日：2018-09-11

申请号：US15479294

申请日：2017-04-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho ,  Wen-Chieh Lu ,  Li-Wei Liu

IPC: H01L27/108

Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.