公开(公告)号：US09530834B1

公开(公告)日：2016-12-27

申请号：US14967344

申请日：2015-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L29/94 ,  H01L49/02

CPC classification number: H01L28/91 ,  H01L28/92

Abstract: A method for fabricating capacitor is disclosed. The method includes the steps of: providing a material layer; forming a patterned first conductive layer on the material layer, forming a first dielectric layer on the patterned first conductive layer; forming a second conductive layer and a cap layer on the first dielectric layer; removing part of the cap layer to form a spacer on the second conductive layer; and using the spacer to remove part of the second conductive layer for forming a trench above the patterned first conductive layer and fin-shaped structures adjacent to the trench.

Abstract translation: 公开了制造电容器的方法。 该方法包括以下步骤：提供材料层; 在所述材料层上形成图案化的第一导电层，在所述图案化的第一导电层上形成第一介电层; 在所述第一介电层上形成第二导电层和盖层; 去除所述盖层的一部分以在所述第二导电层上形成间隔物; 以及使用间隔件去除用于在图案化的第一导电层上方形成沟槽的第二导电层的一部分和与沟槽相邻的鳍状结构。

公开(公告)号：US09412734B2

公开(公告)日：2016-08-09

申请号：US14588991

申请日：2015-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L28/10 ,  H01L28/87 ,  H01L28/91

Abstract: A structure with an inductor and a MIM capacitor is provided. The structure includes a dielectric layer, an inductor and a MIM capacitor. The inductor and the MIM capacitor are disposed within the dielectric layer. The inductor includes a core and a wire surrounding the core. The MIM capacitor includes a top electrode, a bottom electrode and an insulating layer. The top electrode or the bottom electrode includes a material which forms the core.

Abstract translation: 提供具有电感器和MIM电容器的结构。 该结构包括电介质层，电感器和MIM电容器。 电感器和MIM电容器设置在电介质层内。 电感器包括芯和围绕芯的导线。 MIM电容器包括顶电极，底电极和绝缘层。 顶部电极或底部电极包括形成芯的材料。

公开(公告)号：US20150137323A1

公开(公告)日：2015-05-21

申请号：US14080798

申请日：2013-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating through silicon via (TSV) structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon via (TSV) in the substrate; depositing a liner in the TSV; removing the liner in a bottom of the TSV; and filling a first conductive layer in the TSV for forming a TSV structure.

Abstract translation: 公开了一种通过硅通孔（TSV）制造方法。 该方法包括以下步骤：提供衬底; 在衬底中形成穿硅通孔（TSV）; 在TSV中沉积衬垫; 移除TSV底部的衬垫; 以及在TSV中填充用于形成TSV结构的第一导电层。

公开(公告)号：US20190109199A1

公开(公告)日：2019-04-11

申请号：US15725288

申请日：2017-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： HAI BIAO YAO ,  Shao-Hui Wu ,  Xiang Li ,  HSIAO YU CHIA ,  Yu-Cheng Tung

IPC: H01L29/49 ,  H01L21/225 ,  H01L21/02 ,  H01L29/786 ,  H01L29/04

Abstract: An oxide semiconductor device includes an oxide semiconductor channel layer, a first gate dielectric layer, a first gate electrode, a source electrode, and a drain electrode. The oxide semiconductor channel layer includes a channel region. The first gate dielectric layer is disposed on the oxide semiconductor channel layer. The first gate electrode is disposed on the first gate dielectric layer. The source electrode and the drain electrode are disposed at two opposite sides of the first gate electrode in a first direction respectively. The first gate electrode includes a metal material with a work function higher than 4.7 electron volts (eV). A thickness of the oxide semiconductor channel layer is smaller than one third of a length of the channel region in the first direction.

公开(公告)号：US20190081183A1

公开(公告)日：2019-03-14

申请号：US15784176

申请日：2017-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiang Li ,  Shao-Hui Wu ,  HSIAO YU CHIA ,  Yu-Cheng Tung

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10 ,  H01L29/423

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor channel layer, a second oxide semiconductor channel layer, a gate dielectric layer, and a gate electrode. The first patterned oxide semiconductor channel layer is disposed on the substrate. The second patterned oxide semiconductor channel layer is disposed on the first patterned oxide semiconductor channel layer and covers a side edge of the first patterned oxide semiconductor channel layer. The gate dielectric layer is disposed on the second patterned oxide semiconductor channel layer. A top surface of the second patterned oxide semiconductor channel layer is fully covered by the gate dielectric layer. The gate electrode is disposed on the gate dielectric layer. A projection area of the gate electrode in a thickness direction of the substrate is smaller than a projection area of the second patterned oxide semiconductor channel layer in the thickness direction.

公开(公告)号：US20180358475A1

公开(公告)日：2018-12-13

申请号：US15655847

申请日：2017-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： PENGFEI GUO ,  Shao-Hui Wu ,  HAI BIAO YAO ,  Yu-Cheng Tung ,  Yuanli Ding ,  ZHIBIAO ZHOU

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/49 ,  H01L29/417

CPC classification number: H01L29/78696 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/78391 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device includes a substrate, a source region and a drain region, a gate dielectric layer, and a ferroelectric material layer. The ferroelectric material layer overlaps with the source region and overlaps with the drain region. The substrate further comprises a channel layer. A gate electrode is disposed on the substrate. The ferroelectric material layer is disposed between the channel layer and the gate electrode.

公开(公告)号：US10103273B2

公开(公告)日：2018-10-16

申请号：US15447081

申请日：2017-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/24 ,  H01L29/04 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06

Abstract: A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.

公开(公告)号：US10102475B1

公开(公告)日：2018-10-16

申请号：US15800083

申请日：2017-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yun-Yuan Wang ,  Shao-Hui Wu

IPC: G06N3/06 ,  G06N3/063

Abstract: A control circuit including a first switch to a third switch, an inverter, a first capacitor and a second capacitor. The first switch includes a first terminal receiving a weighting signal, and a second terminal. The second switch includes a first terminal, a control terminal coupled to the second terminal of the first switch, and a second terminal coupled to a reference voltage terminal. The third switch includes a first terminal coupled to the reference voltage terminal, a control terminal, and a second terminal. The inverter includes an input terminal coupled to a data input terminal, and an output terminal. The first capacitor is coupled between the data input terminal and the control terminal of the second switch. The second capacitor is coupled between the output terminal of the inverter and the control terminal of the third switch.

公开(公告)号：US09966428B2

公开(公告)日：2018-05-08

申请号：US14996244

申请日：2016-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L49/02

CPC classification number: H01L28/91

Abstract: A method for fabricating capacitor is disclosed. The method includes the steps of: providing a material layer; forming a first conductive layer, a first dielectric layer, and a second conductive layer on the material layer; patterning the first dielectric layer and the second conductive layer to form a patterned first dielectric layer and a middle electrode; forming a second dielectric layer on the first conductive layer and the middle electrode; removing part of the second dielectric layer to form a patterned second dielectric layer; forming a third conductive layer on the first conductive layer and the patterned second dielectric layer, wherein the third conductive layer contacts the first conductive layer directly; and removing part of the third conductive layer to expose part of the patterned second dielectric layer.

公开(公告)号：US20170256652A1

公开(公告)日：2017-09-07

申请号：US15059311

申请日：2016-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chen-Bin Lin ,  Ding-Lung Chen ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L21/426 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/426 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/7869

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, agate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.