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公开(公告)号:US20230225120A1
公开(公告)日:2023-07-13
申请号:US17676209
申请日:2022-02-20
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Yu-Jen Yeh , Hung-Hsun Shuai , Chih-Jung Chen
IPC: H01L27/11524 , H01L27/11558 , H01L29/66 , H01L29/423
CPC classification number: H01L27/11524 , H01L27/11558 , H01L29/66825 , H01L29/42328
Abstract: A memory cell includes a substrate, a floating gate on the substrate, a control gate on the floating gate, a first dielectric layer between the floating gate and the control gate, an erase gate merged with the control gate and disposed on a first sidewall of the floating gate, a second dielectric layer between the floating gate and the erase gate, a select gate on an opposite second sidewall of the floating gate, a spacer between the select gate and the control gate and between the select gate and the floating gate, a source doping region in the substrate and adjacent to the first sidewall of the floating gate, and a drain doping region in the substrate and adjacent to the select gate.
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公开(公告)号:US20220336596A1
公开(公告)日:2022-10-20
申请号:US17855700
申请日:2022-06-30
Applicant: United Microelectronics Corp.
Inventor: Chih-Jung Chen , Yu-Jen Yeh
IPC: H01L21/28 , H01L29/66 , H01L21/762 , H01L29/788
Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.
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公开(公告)号:US11456305B2
公开(公告)日:2022-09-27
申请号:US17005285
申请日:2020-08-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Jung Chen , Hung-Hsun Shuai
IPC: H01L21/00 , H01L27/11521 , H01L27/11565 , H01L27/11519 , H01L27/11568
Abstract: A semiconductor memory device includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate electrode. The isolation layer is disposed on the substrate. The trench penetrates through the isolation layer and exposes a part of the substrate. The semiconductor active structure is disposed in the trench, and the floating gate electrode is disposed on the semiconductor active structure. A manufacturing method of the semiconductor memory device includes the following steps. The isolation layer is formed on the substrate. The trench is formed penetrating through the isolation layer and exposing a part of the substrate. The semiconductor active structure is formed in the trench. The floating gate electrode is formed on the semiconductor active structure.
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公开(公告)号:US20210134967A1
公开(公告)日:2021-05-06
申请号:US16670870
申请日:2019-10-31
Applicant: United Microelectronics Corp.
Inventor: Chih-Jung Chen , Yu-Jen Yeh
IPC: H01L21/28 , H01L29/788 , H01L21/762 , H01L29/66
Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.
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公开(公告)号:US20160049413A1
公开(公告)日:2016-02-18
申请号:US14489439
申请日:2014-09-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Jung Chen , Tzu-Ping Chen
IPC: H01L27/115 , H01L29/66 , G11C16/14 , H01L21/28 , G11C16/04 , G11C16/10 , H01L29/788 , H01L29/40
CPC classification number: H01L29/7887 , G11C16/0408 , G11C16/0416 , G11C16/0466 , G11C16/10 , G11C16/14 , H01L21/28273 , H01L21/28282 , H01L27/11524 , H01L29/42328 , H01L29/66825 , H01L29/7881
Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a floating gate on the substrate; a first silicon oxide layer between the floating gate and the substrate; a first tunnel oxide layer and a second tunnel oxide layer adjacent to two sides of the first silicon oxide layer; and a control gate on the floating gate. Preferably, the thickness of the first tunnel oxide layer and the second tunnel oxide layer is less than the thickness of the first silicon oxide layer.
Abstract translation: 公开了一种半导体器件。 半导体器件包括:衬底; 衬底上的浮动栅极; 在浮置栅极和衬底之间的第一氧化硅层; 与第一氧化硅层的两侧相邻的第一隧道氧化物层和第二隧道氧化物层; 和浮动门上的控制门。 优选地,第一隧道氧化物层和第二隧道氧化物层的厚度小于第一氧化硅层的厚度。
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