公开(公告)号：US20150008504A1

公开(公告)日：2015-01-08

申请号：US13935570

申请日：2013-07-05

Applicant: United Microelectronics Corp.

Inventor： Chun-Lung Chang ,  Tzu-Ping Chen ,  Chih-Haw Lee ,  Kuan-Yi Tseng ,  Chih-Jung Chen ,  Chien-Hung Chen

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/66833 ,  H01L29/40117 ,  H01L29/42348 ,  H01L29/7923

Abstract: A non-volatile memory structure includes a substrate, a gate electrode formed on the substrate, conductive spacers respectively formed on two sides of the gate electrode, and an oxide-nitride-oxide (ONO) structure having an inverted T shape formed on the substrate. The gate electrode includes a gate conductive layer and a gate dielectric layer. The ONO structure includes a base portion and a body portion. The base portion of the ONO structure is sandwiched between the gate electrode and the substrate, and between the conductive spacer and the substrate. The body portion of the T-shaped ONO structure is upwardly extended from the base portion and sandwiched between the gate electrode and the conductive spacer.

Abstract translation: 非易失性存储器结构包括：衬底，形成在衬底上的栅极电极，分别形成在栅电极的两侧上的导电衬垫和在衬底上形成有倒T形的氧化物 - 氧化物（ONO）结构 。 栅电极包括栅极导电层和栅极电介质层。 ONO结构包括基部和主体部分。 ONO结构的基部被夹在栅电极和衬底之间以及导电间隔物和衬底之间。 T形ONO结构的主体部分从基部向上延伸并夹在栅电极和导电间隔件之间。

公开(公告)号：US20240324197A1

公开(公告)日：2024-09-26

申请号：US18306231

申请日：2023-04-24

Applicant: United Microelectronics Corp.

Inventor： Hung Hsun Shuai ,  Chih-Jung Chen

IPC: H10B41/40 ,  H01L23/60 ,  H10B41/30

CPC classification number: H10B41/40 ,  H01L23/60 ,  H10B41/30

Abstract: A semiconductor device includes a substrate, a doped ring, a plurality of contacts, and a plurality of conductive lines. The substrate includes a first region and a second region surrounding the first region. The doped ring is located in the substrate in the second region and surrounds the first region. The doped ring includes a first doped region and a plurality of second doped regions. The first doped region is located in the substrate in the second region and surrounds the first region. The first doped region has an opening. The second doped regions are separated from each other and located in the substrate of the opening. The contacts are electrically connected to the second doped regions. The conductive lines are connected to the contacts and a plurality of conductive layers in the first region.

公开(公告)号：US11417734B2

公开(公告)日：2022-08-16

申请号：US16670870

申请日：2019-10-31

Applicant: United Microelectronics Corp.

Inventor： Chih-Jung Chen ,  Yu-Jen Yeh

IPC: H01L21/762 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3105

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

公开(公告)号：US20220209017A1

公开(公告)日：2022-06-30

申请号：US17159168

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Hsun Shuai ,  Chih-Jung Chen

IPC: H01L29/788 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/265 ,  H01L21/762 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor memory device includes a substrate having a first active area and a second active area in proximity to the first active area. A trench isolation region is between the first active area and the second active area. A source line region is disposed in the first active area and adjacent to the trench isolation region. An erase gate is disposed on the source line region. A floating gate is disposed on a first side of the erase gate. A first control gate is disposed on the floating gate. A first word line is disposed adjacent to the floating gate and the first control gate and insulated therefrom. A second control gate is disposed on a second side of the erase gate and directly on the trench isolation region. A second word line is disposed adjacent to the second control gate and insulated therefrom.

公开(公告)号：US10243084B2

公开(公告)日：2019-03-26

申请号：US15279410

申请日：2016-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Jung Chen ,  Tzu-Ping Chen

IPC: H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L29/423

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a dielectric stack is formed on the substrate, in which the dielectric stack includes a first silicon oxide layer and a first silicon nitride layer. Next, the dielectric stack is patterned, part of the first silicon nitride layer is removed to form two recesses under two ends of the first silicon nitride layer, second silicon oxide layers are formed in the two recesses, a spacer is formed on the second silicon oxide layers, and third silicon oxide layers are formed adjacent to the second silicon oxide layers.

公开(公告)号：US09490016B2

公开(公告)日：2016-11-08

申请号：US14489439

申请日：2014-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Jung Chen ,  Tzu-Ping Chen

IPC: H01L29/788 ,  G11C16/14 ,  H01L29/66 ,  H01L21/28 ,  G11C16/04 ,  G11C16/10 ,  H01L27/115

CPC classification number: H01L29/7887 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a floating gate on the substrate; a first silicon oxide layer between the floating gate and the substrate; a first tunnel oxide layer and a second tunnel oxide layer adjacent to two sides of the first silicon oxide layer; and a control gate on the floating gate. Preferably, the thickness of the first tunnel oxide layer and the second tunnel oxide layer is less than the thickness of the first silicon oxide layer.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 衬底上的浮动栅极; 在浮置栅极和衬底之间的第一氧化硅层; 与第一氧化硅层的两侧相邻的第一隧道氧化物层和第二隧道氧化物层; 和浮动门上的控制门。 优选地，第一隧道氧化物层和第二隧道氧化物层的厚度小于第一氧化硅层的厚度。

公开(公告)号：US20230171958A1

公开(公告)日：2023-06-01

申请号：US17565484

申请日：2021-12-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Hsun Shuai ,  Yu-Jen Yeh ,  Chih-Jung Chen

IPC: H01L27/11526 ,  G11C16/28 ,  G11C16/24

CPC classification number: H01L27/11526 ,  G11C16/28 ,  G11C16/24

Abstract: A semiconductor memory device includes a substrate, a plurality of memory cells and at least one strap cell between the plurality of memory cells disposed along a first direction, a plurality of bit line (BL) contacts electrically connected to a plurality of drain doped regions of the plurality of memory cells, respectively, and at least one source line contact electrically connected to a diffusion region of the strap cell. The at least one source line contact is aligned with the plurality of BL contacts in the first direction.

公开(公告)号：US11637188B2

公开(公告)日：2023-04-25

申请号：US17226431

申请日：2021-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Jen Yeh ,  Chih-Jung Chen

IPC: H10B41/30 ,  H01L29/423 ,  H01L27/11521 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L21/265 ,  H01L21/28

Abstract: An NVM device includes a semiconductor substrate, a first floating gate, a first control gate, a first drain region, and a common source region. The semiconductor substrate has a recess extending downward from the substrate surface. The first floating gate is disposed in the recess, has a base and a side wall connecting to the base. The first control gate is disposed on and adjacent to the first floating gate. The first drain region is disposed in the semiconductor substrate in the recess. The common source region is formed in the semiconductor substrate in the recess, is adjacent to the first floating gate, and includes a main body and an extension part. The main body is disposed below a bottom surface of the recess and adjacent to the base. The extension part extends upward from the bottom surface beyond the base to be adjacent to the side wall.

公开(公告)号：US20220415913A1

公开(公告)日：2022-12-29

申请号：US17888511

申请日：2022-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Jung Chen ,  Hung-Hsun Shuai

IPC: H01L27/11521 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11568

Abstract: A semiconductor memory device includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate electrode. The isolation layer is disposed on the substrate. The trench penetrates through the isolation layer and exposes a part of the substrate. The semiconductor active structure is disposed in the trench, and the floating gate electrode is disposed on the semiconductor active structure. A manufacturing method of the semiconductor memory device includes the following steps. The isolation layer is formed on the substrate. The trench is formed penetrating through the isolation layer and exposing a part of the substrate. The semiconductor active structure is formed in the trench. The floating gate electrode is formed on the semiconductor active structure.

公开(公告)号：US11495693B2

公开(公告)日：2022-11-08

申请号：US17159168

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Hsun Shuai ,  Chih-Jung Chen

IPC: H01L29/788 ,  H01L21/265 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor memory device includes a substrate having a first active area and a second active area in proximity to the first active area. A trench isolation region is between the first active area and the second active area. A source line region is disposed in the first active area and adjacent to the trench isolation region. An erase gate is disposed on the source line region. A floating gate is disposed on a first side of the erase gate. A first control gate is disposed on the floating gate. A first word line is disposed adjacent to the floating gate and the first control gate and insulated therefrom. A second control gate is disposed on a second side of the erase gate and directly on the trench isolation region. A second word line is disposed adjacent to the second control gate and insulated therefrom.