公开(公告)号：US11707003B2

公开(公告)日：2023-07-18

申请号：US17140981

申请日：2021-01-04

Applicant: United Microelectronics Corp.

Inventor： Chich-Neng Chang ,  Da-Jun Lin ,  Shih-Wei Su ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/24 ,  H10B63/30 ,  H10N70/063 ,  H10N70/826 ,  H10N70/841

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

公开(公告)号：US11688802B2

公开(公告)日：2023-06-27

申请号：US17179322

申请日：2021-02-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Chang ,  Yao-Hsien Chung ,  Shih-Wei Su ,  Hao-Hsuan Chang ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462

Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is then subjected to an oxidation treatment or a nitridation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.

公开(公告)号：US20230135072A1

公开(公告)日：2023-05-04

申请号：US18090510

申请日：2022-12-29

Applicant: United Microelectronics Corp.

Inventor： Hao Che Feng ,  Hung Jen Huang ,  Hsin Min Han ,  Shih-Wei Su ,  Ming Shu Chiu ,  Pi-Hung Chuang ,  Wei-Hao Huang ,  Shao-Wei Wang ,  Ping Wei Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

Abstract: The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.

公开(公告)号：US11043596B2

公开(公告)日：2021-06-22

申请号：US16451018

申请日：2019-06-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Hao-Hsuan Chang ,  Chih-Wei Chang ,  Chi-Hsuan Cheng ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A method for forming a semiconductor device is disclosed. A substrate having at least two fins thereon and an isolation trench between the at least two fins is provided. A liner layer is then deposited on the substrate. The liner layer conformally covers the two fins and interior surface of the isolation trench. A stress-buffer film is then deposited on the liner layer. The stress-buffer film completely fills a lower portion that is located at least below half of a trench depth of the isolation trench. A trench-fill oxide layer is then deposited to completely fill an upper portion of the isolation trench.

公开(公告)号：US12015076B2

公开(公告)日：2024-06-18

申请号：US18092916

申请日：2023-01-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Chang ,  Yao-Hsien Chung ,  Shih-Wei Su ,  Hao-Hsuan Chang ,  Da-Jun Lin ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/7786

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed on the gate.

公开(公告)号：US20230301210A1

公开(公告)日：2023-09-21

申请号：US18324173

申请日：2023-05-26

Applicant: United Microelectronics Corp.

Inventor： Chich-Neng Chang ,  Da-Jun Lin ,  Shih-Wei Su ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/24 ,  H10B63/30 ,  H10N70/063 ,  H10N70/826 ,  H10N70/841

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

公开(公告)号：US11762293B2

公开(公告)日：2023-09-19

申请号：US17316736

申请日：2021-05-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Da-Jun Lin ,  Yao-Hsien Chung ,  Ting-An Chien ,  Bin-Siang Tsai ,  Chih-Wei Chang ,  Shih-Wei Su ,  Hsu Ting ,  Sung-Yuan Tsai

IPC: G03F7/075 ,  G03F7/20 ,  C23C16/34

CPC classification number: G03F7/0755 ,  G03F7/2043 ,  C23C16/345

Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.

公开(公告)号：US20230163207A1

公开(公告)日：2023-05-25

申请号：US17834936

申请日：2022-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Chang ,  Da-Jun Lin ,  Yao-Hsien Chung ,  Shih-Wei Su ,  Hao-Hsuan Chang ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462

Abstract: The invention provides a semiconductor structure, which comprises a GaN gallium nitride (GaN) layer, an aluminum gallium nitride (AlGaN) layer on the gallium nitride layer, a polarization boost layer on and in direct contact with the aluminum gallium nitride layer, and a gate liner layer on the polarization boost layer.

公开(公告)号：US11495737B2

公开(公告)日：2022-11-08

申请号：US16916037

申请日：2020-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Shih-Wei Su ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.

公开(公告)号：US20220173311A1

公开(公告)日：2022-06-02

申请号：US17140981

申请日：2021-01-04

Applicant: United Microelectronics Corp.

Inventor： Chich-Neng Chang ,  Da-Jun Lin ,  Shih-Wei Su ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.