公开(公告)号：US20150087126A1

公开(公告)日：2015-03-26

申请号：US14557469

申请日：2014-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Yu-Shu Lin ,  Jei-Ming Chen ,  Wen-Yi Teng

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/324 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653

Abstract: A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.) . Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer.

Abstract translation: 一种制造具有不均匀应力层的晶体管器件的方法，包括以下过程。 首先，提供具有第一晶体管区域的半导体衬底。 进行低温沉积工艺以在第一晶体管区域内的晶体管上形成第一拉伸应力层，其中低温沉积工艺的温度低于300摄氏度（℃）。 然后，进行高温退火处理，其中高温退火工艺的温度比低温沉积工艺的温度高至少150℃。 最后，在第一拉伸应力层上形成第二拉伸应力层，其中第一拉伸应力层的拉伸应力低于第二拉伸应力层的拉伸应力。

公开(公告)号：US20240332086A1

公开(公告)日：2024-10-03

申请号：US18739261

申请日：2024-06-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Po-Ching Su ,  Yu-Fu Wang ,  Min-Hua Tsai ,  Ti-Bin Chen ,  Chih-Chiang Wu ,  Tzu-Chin Wu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/4232 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

公开(公告)号：US10770464B2

公开(公告)日：2020-09-08

申请号：US15896091

申请日：2018-02-14

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Chia-Lung Chang ,  Tzu-Chin Wu ,  Wei-Lun Hsu

IPC: H01L23/532 ,  H01L27/108

Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.

公开(公告)号：US10672864B2

公开(公告)日：2020-06-02

申请号：US16297733

申请日：2019-03-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Po-Chun Chen ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Wen-Chieh Lu ,  Chien-Ting Ho ,  Tsung-Ying Tsai ,  Kai-Ping Chen

IPC: H01L49/02 ,  H01L29/94 ,  H01L27/108

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.

公开(公告)号：US10446559B2

公开(公告)日：2019-10-15

申请号：US16053748

申请日：2018-08-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Chao-An Liu ,  Ching-Hsiang Chang ,  Yi-Wei Chen

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/02 ,  H01L21/306 ,  H01L21/033 ,  H01L21/027

Abstract: A method of fabricating a DRAM includes providing a substrate. Later, a first mask layer is formed to cover the substrate. The first mask layer includes a hydrogen-containing silicon nitride layer and a silicon oxide layer. The hydrogen-containing silicon nitride layer has the chemical formula: SixNyHz, wherein x is between 4 and 8, y is between 3.5 and 9.5, and z equals 1. After that, the first mask layer is patterned to form a first patterned mask layer. Next, the substrate is etched by taking the first patterned mask layer as a mask to form a word line trench. Subsequently, the first patterned mask layer is removed entirely. Finally, a word line is formed in the word line trench.

公开(公告)号：US20190221570A1

公开(公告)日：2019-07-18

申请号：US15896091

申请日：2018-02-14

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Chia-Lung Chang ,  Tzu-Chin Wu ,  Wei-Lun Hsu

IPC: H01L27/108 ,  H01L23/532

Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.

公开(公告)号：US10332888B2

公开(公告)日：2019-06-25

申请号：US15810145

申请日：2017-11-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Chia-Lung Chang ,  Han-Yung Tsai ,  Tzu-Chin Wu

IPC: H01L21/285 ,  H01L27/108

Abstract: A method of manufacturing memory devices is provided in the present invention. The method includes the steps of providing a substrate with multiple capacitors, wherein the capacitor includes a lower electrode layer, an insulating layer and an upper electrode layer and a top plate, forming a tungsten layer on the upper electrode, performing a nitriding plasma treatment to the tungsten layer to form a tungsten nitride layer, and forming a pre-metal dielectric layer on the tungsten nitride layer.

公开(公告)号：US10312080B2

公开(公告)日：2019-06-04

申请号：US15859750

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Mei-Ling Chen ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Ching-Hsiang Chang ,  Jui-Min Lee ,  Chia-Lung Chang ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L21/02

Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.

公开(公告)号：US20180308923A1

公开(公告)日：2018-10-25

申请号：US15927103

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Po-Chun Chen ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Wen-Chieh Lu ,  Chien-Ting Ho ,  Tsung-Ying Tsai ,  Kai-Ping Chen

IPC: H01L49/02 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L28/82 ,  H01L27/10808 ,  H01L27/10855 ,  H01L28/87 ,  H01L29/94

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.

公开(公告)号：US08937369B2

公开(公告)日：2015-01-20

申请号：US13633094

申请日：2012-10-01

Applicant: United Microelectronics Corp.

Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Yu-Shu Lin ,  Jei-Ming Chen ,  Wen-Yi Teng

IPC: H01L23/58 ,  H01L21/469

CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653

Abstract: A transistor includes a semiconductor substrate, at least a gate structure, at least a first tensile stress layer, a second tensile stress layer, a source region, and a drain region. The gate structure is disposed within a first transistor region of the semiconductor substrate. The first tensile stress layer includes a curved portion encompassing the gate structure, at least an extension portion with a curved top surface located on the semiconductor substrate at sides of the gate structure, and a transition portion between the curved portion and the extension portion. The first tensile stress layer has a thickness gradually thinning from the curved portion and the extension portion toward the transition portion. The second tensile stress layer is disposed on the first tensile stress layer. And the source/drain regions are separately located in the semiconductor substrate on two sides of the gate structure.

Abstract translation: 晶体管包括半导体衬底，至少栅极结构，至少第一拉伸应力层，第二拉伸应力层，源极区和漏极区。 栅极结构设置在半导体衬底的第一晶体管区域内。 第一拉伸应力层包括包围栅极结构的弯曲部分，至少一个在栅极结构的侧面处位于半导体衬底上的弯曲顶表面的延伸部分和弯曲部分与延伸部分之间的过渡部分。 第一拉伸应力层具有从弯曲部分和延伸部分朝向过渡部分逐渐变薄的厚度。 第二拉伸应力层设置在第一拉伸应力层上。 并且源极/漏极区域分别位于栅极结构两侧的半导体衬底中。