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    METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE
    1.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20210257471A1

    公开(公告)日：2021-08-19

    申请号：US17246726

    申请日：2021-05-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Fan Li ,  Kuo-Chin Hung ,  Wen-Yi Teng ,  Ti-Bin Chen

    IPC: H01L29/417 ,  H01L29/49 ,  H01L29/423 ,  H01L21/311 ,  H01L29/66 ,  H01L29/161 ,  H01L29/78

    Abstract: A first gate and a second gate are formed on a substrate with a gap between the first and second gates. The first gate has a first sidewall. The second gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.

    SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME 审中-公开

    公开(公告)号：US20190198628A1

    公开(公告)日：2019-06-27

    申请号：US15853867

    申请日：2017-12-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Fan Li ,  Kuo-Chin Hung ,  Wen-Yi Teng ,  Ti-Bin Chen

    IPC: H01L29/417 ,  H01L29/49 ,  H01L29/423 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311

    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes first and second metal gates on a substrate with a gap therebetween. The first metal gate has a first sidewall, and the second metal gate has a second sidewall directly facing the first sidewall. A contact etch stop layer (CESL) is disposed within the gap and extends along the first and second sidewalls. The CESL has a first top portion adjacent to a top surface of the first metal gate and a second top portion adjacent to a top surface of the second metal gate. The first top portion and the second top portion have a trapezoid cross-sectional profile. A first sidewall spacer is disposed on the first sidewall and between the CESL and the first metal gate. A second sidewall spacer is disposed on the second sidewall and between the CESL and the second metal gate.

    METHOD OF FABRICATION TRANSISTOR WITH NON-UNIFORM STRESS LAYER WITH STRESS CONCENTRATED REGIONS
    3.
    发明申请
    METHOD OF FABRICATION TRANSISTOR WITH NON-UNIFORM STRESS LAYER WITH STRESS CONCENTRATED REGIONS 有权
    具有应力集中区域的非均匀应力层制造晶体的方法

    公开(公告)号：US20150087126A1

    公开(公告)日：2015-03-26

    申请号：US14557469

    申请日：2014-12-02

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Yu-Shu Lin ,  Jei-Ming Chen ,  Wen-Yi Teng

    IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/324 ,  H01L29/78

    CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653

    Abstract: A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.) . Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer.

    Abstract translation: 一种制造具有不均匀应力层的晶体管器件的方法，包括以下过程。 首先，提供具有第一晶体管区域的半导体衬底。 进行低温沉积工艺以在第一晶体管区域内的晶体管上形成第一拉伸应力层，其中低温沉积工艺的温度低于300摄氏度（℃）。 然后，进行高温退火处理，其中高温退火工艺的温度比低温沉积工艺的温度高至少150℃。 最后，在第一拉伸应力层上形成第二拉伸应力层，其中第一拉伸应力层的拉伸应力低于第二拉伸应力层的拉伸应力。

    METHOD FOR FORMING ISOLATION STRUCTURE
    4.
    发明申请
    METHOD FOR FORMING ISOLATION STRUCTURE 审中-公开
    形成隔离结构的方法

    公开(公告)号：US20140213034A1

    公开(公告)日：2014-07-31

    申请号：US13752408

    申请日：2013-01-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Lung Chang ,  Chih-Chien Liu ,  Jei-Ming Chen ,  Wen-Yi Teng ,  Jui-Min Lee ,  Keng-Jen Lin ,  Chin-Fu Lin

    IPC: H01L21/762

    CPC classification number: H01L21/76224 ,  H01L21/76232

    Abstract: A method for forming an isolation structure includes the following steps. A hard mask layer is formed on a substrate and a trench is formed in the substrate and the hard mask layer. A protective layer is formed to cover the trench and the hard mask layer. A first isolation material is filled into the trench. An etching process is performed to etch back part of the first isolation material.

    Abstract translation: 形成隔离结构的方法包括以下步骤。 在基板上形成硬掩模层，并且在基板和硬掩模层中形成沟槽。 形成保护层以覆盖沟槽和硬掩模层。 第一隔离材料被填充到沟槽中。 执行蚀刻工艺以蚀刻第一隔离材料的一部分。

    Method of forming an isolation structure
    6.
    发明授权
    Method of forming an isolation structure 有权
    形成隔离结构的方法

    公开(公告)号：US08709901B1

    公开(公告)日：2014-04-29

    申请号：US13864277

    申请日：2013-04-17

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Lung Chang ,  Wu-Sian Sie ,  Jei-Ming Chen ,  Wen-Yi Teng ,  Chih-Chien Liu ,  Jui-Min Lee ,  Chih-Hsun Lin

    IPC: H01L21/336

    CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/32105

    Abstract: The present invention relates to a method of forming an isolation structure, in which, a trench is formed in a substrate through a hard mask, and deposition, etch back, deposition, planarization, and etch back are performed in the order to form an isolation material layer of the isolation structure after the hard mask is removed. A silicon layer may be formed to cover the trench and original surface of the substrate before the former deposition, or to cover a part of the trench and original surface of the substrate after the former etch back and before the later deposition, to serve as a stop layer for the planarization process. Voids existing within the isolation material layer can be exposed or removed by partially etching the isolation material layer by the former etch back. The later deposition can be performed with a less aspect ratio to avoid forming voids.

    Abstract translation: 本发明涉及一种形成隔离结构的方法，其中通过硬掩模在衬底中形成沟槽，并且进行沉积，回蚀刻，沉积，平坦化和回蚀以形成隔离 去除硬掩模后隔离结构的材料层。 可以形成硅层以在前一次沉积之前覆盖衬底的沟槽和原始表面，或者在前面的回蚀刻和稍后的沉积之前覆盖衬底的一部分沟槽和原始表面，以用作 停止层进行平面化处理。 存在于隔离材料层内的空隙可以通过由前面的回蚀部分蚀刻隔离材料层而被暴露或去除。 可以以较小的纵横比进行后续沉积以避免形成空隙。

    TRANSISTOR
    7.
    发明申请
    TRANSISTOR 有权
    晶体管

    公开(公告)号：US20140091395A1

    公开(公告)日：2014-04-03

    申请号：US13633094

    申请日：2012-10-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Yu-Shu Lin ,  Jei-Ming Chen ,  Wen-Yi Teng

    IPC: H01L21/336 ,  H01L27/088 ,  H01L21/28

    CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653

    Abstract: A method for fabricating a transistor device including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a lower tensile stress than the second tensile stress layer.

    Abstract translation: 一种晶体管器件的制造方法，包括以下工序。 首先，提供具有第一晶体管区域的半导体衬底。 进行低温沉积工艺以在第一晶体管区域内的晶体管上形成第一拉伸应力层，其中低温沉积工艺的温度低于300摄氏度（℃）。 然后，进行高温退火处理，其中高温退火工艺的温度比低温沉积工艺的温度高至少150℃。 最后，在第一拉伸应力层上形成第二拉伸应力层，其中第一拉伸应力层具有比第二拉伸应力层低的拉伸应力。

    POLYSILICON LAYER
    8.
    发明申请
    POLYSILICON LAYER 审中-公开
    多晶硅层

    公开(公告)号：US20150021776A1

    公开(公告)日：2015-01-22

    申请号：US14507317

    申请日：2014-10-06

    Applicant: United Microelectronics Corp.

    Inventor： Chien-Liang Lin ,  Yu-Ren Wang ,  Ying-Wei Yen ,  Wen-Yi Teng ,  Chan-Lon Yang

    IPC: H01L29/49

    CPC classification number: H01L29/4916 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28035 ,  H01L29/4925

    Abstract: A polysilicon layer including an amorphous polysilicon layer and a crystallized polysilicon layer is provided. The crystallized polysilicon layer is disposed on the amorphous polysilicon layer. Besides, the amorphous polysilicon layer has a first grain size, the crystallized polysilicon layer has a second grain size, and the first grain size is smaller than the second grain size. The amorphous polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the crystallized polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.

    Abstract translation: 提供了包括非晶多晶硅层和结晶的多晶硅层的多晶硅层。 结晶的多晶硅层设置在非晶多晶硅层上。 此外，非晶多晶硅层具有第一晶粒尺寸，结晶的多晶硅层具有第二晶粒尺寸，并且第一晶粒尺寸小于第二晶粒尺寸。 具有较小晶粒尺寸的非晶多晶硅层可以用作随后沉积的基底，使得其上形成的结晶多晶硅层具有更平坦的形貌，因此表面粗糙度降低，晶片内的Rs均匀性提高。

    Transistor with non-uniform stress layer with stress concentrated regions
    9.
    发明授权
    Transistor with non-uniform stress layer with stress concentrated regions 有权
    具有应力集中区域的不均匀应力层的晶体管

    公开(公告)号：US08937369B2

    公开(公告)日：2015-01-20

    申请号：US13633094

    申请日：2012-10-01

    Applicant: United Microelectronics Corp.

    Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Yu-Shu Lin ,  Jei-Ming Chen ,  Wen-Yi Teng

    IPC: H01L23/58 ,  H01L21/469

    CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653

    Abstract: A transistor includes a semiconductor substrate, at least a gate structure, at least a first tensile stress layer, a second tensile stress layer, a source region, and a drain region. The gate structure is disposed within a first transistor region of the semiconductor substrate. The first tensile stress layer includes a curved portion encompassing the gate structure, at least an extension portion with a curved top surface located on the semiconductor substrate at sides of the gate structure, and a transition portion between the curved portion and the extension portion. The first tensile stress layer has a thickness gradually thinning from the curved portion and the extension portion toward the transition portion. The second tensile stress layer is disposed on the first tensile stress layer. And the source/drain regions are separately located in the semiconductor substrate on two sides of the gate structure.

    Abstract translation: 晶体管包括半导体衬底，至少栅极结构，至少第一拉伸应力层，第二拉伸应力层，源极区和漏极区。 栅极结构设置在半导体衬底的第一晶体管区域内。 第一拉伸应力层包括包围栅极结构的弯曲部分，至少一个在栅极结构的侧面处位于半导体衬底上的弯曲顶表面的延伸部分和弯曲部分与延伸部分之间的过渡部分。 第一拉伸应力层具有从弯曲部分和延伸部分朝向过渡部分逐渐变薄的厚度。 第二拉伸应力层设置在第一拉伸应力层上。 并且源极/漏极区域分别位于栅极结构两侧的半导体衬底中。

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