公开(公告)号：US20220384710A1

公开(公告)日：2022-12-01

申请号：US17361331

申请日：2021-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Jin-Yan Chiou ,  Hsiang-Wen Ke

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming a first top electrode on the MTJ stack, and then forming a second top electrode on the first top electrode. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.

公开(公告)号：US20210050253A1

公开(公告)日：2021-02-18

申请号：US16568266

申请日：2019-09-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Li-Han Chen ,  Hsiang-Wen Ke

IPC: H01L21/768 ,  H01L21/285 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to two sides of the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a contact hole in the ILD layer to expose the source/drain region; forming a barrier layer in the contact hole; performing an anneal process; and performing a plasma treatment process to inject nitrogen into the contact hole.

公开(公告)号：US20200006517A1

公开(公告)日：2020-01-02

申请号：US16053665

申请日：2018-08-02

Applicant: United Microelectronics Corp.

Inventor： Yi-Fan Li ,  Po-Ching Su ,  Cheng-Chia Liu ,  Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Chih-Chiang Wu ,  Ti-Bin Chen ,  Ching-Chu Tseng

IPC: H01L29/66 ,  H01L29/78 ,  H01L23/31

Abstract: A structure of semiconductor device includes a gate structure, disposed on a substrate. A spacer is disposed on a sidewall of the gate structure, wherein the spacer is an l-like structure. A first doped region is disposed in the substrate at two sides of the gate structure. A second doped region is disposed in the substrate at the two sides of the gate structure, overlapping the first doped region. A silicide layer is disposed on the substrate within the second doped region, separating from the spacer by a distance. A dielectric layer covers over the second doped region and the gate structure with the spacer.

公开(公告)号：US10199269B2

公开(公告)日：2019-02-05

申请号：US15361503

申请日：2016-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Han Chen ,  Yen-Tsai Yi ,  Chun-Chieh Chiu ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Hsin-Fu Huang

IPC: H01L23/485 ,  H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78

Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.

公开(公告)号：US20180366368A1

公开(公告)日：2018-12-20

申请号：US15626168

申请日：2017-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Chieh Chiu ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Li-Han Chen

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: The present invention provides a method for forming a contact structure, the method includes proving a substrate. An oxygen-containing dielectric layer is formed on the substrate. Next, a non-oxygen layer is formed on the oxygen-containing dielectric layer and a contact hole is then formed in the oxygen-containing dielectric layer. A metal layer is then formed in the contact hole and on the non-oxygen layer, with the non-oxygen layer disposed between the oxygen-containing dielectric layer and the metal layer. An anneal process is then performed to the metal layer, and a conductive layer is filled in the contact hole.