公开(公告)号：US11450564B2

公开(公告)日：2022-09-20

申请号：US16568266

申请日：2019-09-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Li-Han Chen ,  Hsiang-Wen Ke

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/285

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to two sides of the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a contact hole in the ILD layer to expose the source/drain region; forming a barrier layer in the contact hole; performing an anneal process; and performing a plasma treatment process to inject nitrogen into the contact hole.

公开(公告)号：US09640482B1

公开(公告)日：2017-05-02

申请号：US15097301

申请日：2016-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Min-Chuan Tsai ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Kuo-Chin Hung ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L29/45 ,  H01L23/522

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266

Abstract: The present invention utilizes a barrier layer in the contact hole to react with an S/D region to form a silicide layer. After forming the silicide layer, a directional deposition process is performed to form a first metal layer primarily on the barrier layer at the bottom of the contact hole, so that very little or even no first metal layer is disposed on the barrier layer at the sidewall of the contact hole. Then, the second metal layer is deposited from bottom to top in the contact hole as the deposition rate of the second metal layer on the barrier layer is slower than the deposition rate of the second metal layer on the first metal layer.

公开(公告)号：US20230125856A1

公开(公告)日：2023-04-27

申请号：US17533146

申请日：2021-11-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiang-Wen Ke ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Jin-Yan Chiou

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L27/22

Abstract: A method for fabricating a semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a barrier layer in the trench, forming a nucleation layer on the barrier layer, performing an anneal process to form a silicide layer, forming a bulk layer on the silicide layer, and forming a magnetic tunneling junction (MTJ) on the bulk layer.

公开(公告)号：US20210343931A1

公开(公告)日：2021-11-04

申请号：US16882552

申请日：2020-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

公开(公告)号：US20190057895A1

公开(公告)日：2019-02-21

申请号：US15711854

申请日：2017-09-21

Applicant: United Microelectronics Corp.

Inventor： Li-Han Chen ,  Chun-Chieh Chiu ,  Wei-Chuan Tsai ,  Yen-Tsai Yi

IPC: H01L21/74 ,  H01L21/768

Abstract: A manufacturing method of an interconnect structure including the following steps is provided. A dielectric layer is formed on a silicon layer, wherein an opening exposing the silicon layer is in the dielectric layer. A metal layer is formed on the surface of the opening. A stress adjustment layer is formed on the metal layer. A thermal process is performed to react the metal layer with the silicon layer to form a metal silicide layer on the silicon layer. The stress adjustment layer is removed after the thermal process is performed. A barrier layer is formed on the surface of the opening.

公开(公告)号：US20250089448A1

公开(公告)日：2025-03-13

申请号：US18381646

申请日：2023-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Jin-Yan Chiou ,  Hsiang-Wen Ke

IPC: H10K50/81 ,  H10K50/11 ,  H10K50/82 ,  H10K50/856 ,  H10K59/131

Abstract: An organic light-emitting diode display device includes a first light-emitting layer, a first anode, a first reflective pattern, and a dielectric material. The first light-emitting layer, the first anode, and the first reflective pattern are located in a first sub-pixel region. The first anode is disposed under the first light-emitting layer in a vertical direction, and the first reflective pattern is disposed under the first anode in the vertical direction. The dielectric material is partly disposed between the first anode and the first reflective pattern, and the first reflective pattern is electrically connected with the first anode.

公开(公告)号：US20240397832A1

公开(公告)日：2024-11-28

申请号：US18791383

申请日：2024-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Jin-Yan Chiou ,  Hsiang-Wen Ke

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunneling junction (MTJ) on a substrate, a first top electrode on the MTJ, a second top electrode on and directly contacting the first top electrode, and a spacer adjacent to the MTJ. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.

公开(公告)号：US20240237549A1

公开(公告)日：2024-07-11

申请号：US18610212

申请日：2024-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H10N50/80 ,  G11C11/16 ,  H01F10/32 ,  H01F41/32 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10N50/01 ,  H01F10/3254 ,  H01F41/32 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

公开(公告)号：US11968906B2

公开(公告)日：2024-04-23

申请号：US16882552

申请日：2020-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H10N50/80 ,  G11C11/16 ,  H10N50/01 ,  H10N50/85 ,  H01F10/32 ,  H01F41/32

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10N50/01 ,  H01F10/3254 ,  H01F41/32 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

公开(公告)号：US20230387280A1

公开(公告)日：2023-11-30

申请号：US17851048

申请日：2022-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Jin-Yan Chiou ,  Hsiang-Wen Ke

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7783 ,  H01L29/2003 ,  H01L29/0847 ,  H01L29/66462

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a titanium nitride (TiN) layer on the p-type semiconductor layer as a nitrogen to titanium (N/Ti) ratio of the TiN layer is greater than 1, forming a passivation layer on the TiN layer and the barrier layer, removing the passivation layer to form an opening, forming a gate electrode in the opening, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode on the buffer layer.