公开(公告)号：US20240332086A1

公开(公告)日：2024-10-03

申请号：US18739261

申请日：2024-06-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Po-Ching Su ,  Yu-Fu Wang ,  Min-Hua Tsai ,  Ti-Bin Chen ,  Chih-Chiang Wu ,  Tzu-Chin Wu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/4232 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

公开(公告)号：US11757016B2

公开(公告)日：2023-09-12

申请号：US17709385

申请日：2022-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L27/092

CPC classification number: H01L29/4966 ,  H01L27/092 ,  H01L29/401

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US20220223710A1

公开(公告)日：2022-07-14

申请号：US17709385

申请日：2022-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L27/092

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US20250089334A1

公开(公告)日：2025-03-13

申请号：US18379674

申请日：2023-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Chen-Ming Wang ,  Po-Ching Su ,  Pei-Hsun Kao ,  Ti-Bin Chen ,  Chun-Wei Yu ,  Chih-Chiang Wu

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor includes a substrate. A gate structure is disposed on the substrate. A liner oxide contacts a side of the gate structure. A silicon oxide spacer contacts the liner oxide. An end of the silicon oxide spacer forms a kink profile. A silicon nitride spacer contacts the silicon oxide spacer and a tail of the silicon nitride spacer covers part of the kink profile. A stressor covers the silicon nitride spacer and the substrate.

公开(公告)号：US11031477B2

公开(公告)日：2021-06-08

申请号：US16701122

申请日：2019-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Kuo-Chin Hung ,  Wen-Yi Teng ,  Ti-Bin Chen

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L21/311 ,  H01L29/161 ,  H01L29/165

Abstract: A first dummy gate and a second dummy gate are formed on a substrate with a gap between the first and second dummy gates. The first dummy gate has a first sidewall. The second dummy gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second dummy gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.

公开(公告)号：US10734496B2

公开(公告)日：2020-08-04

申请号：US16177368

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L27/092

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first bottom barrier metal (BBM) layer on the first region and the second region; forming a first work function metal layer on the first BBM layer on the first region and the second region; removing the first work function metal (WFM) layer and part of the first BBM layer on the second region; and forming a diffusion barrier layer on the first WFM layer on the first region and the first BBM layer on the second region.

公开(公告)号：US20180019324A1

公开(公告)日：2018-01-18

申请号：US15590510

申请日：2017-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Chen Chan ,  Yi-Fan Li ,  Yen-Hsing Chen ,  Chun-Yu Chen ,  Chung-Ting Huang ,  Zih-Hsuan Huang ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

公开(公告)号：US12125890B2

公开(公告)日：2024-10-22

申请号：US18226264

申请日：2023-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/40

CPC classification number: H01L29/4966 ,  H01L27/092 ,  H01L29/401

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US20200111884A1

公开(公告)日：2020-04-09

申请号：US16177368

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first bottom barrier metal (BBM) layer on the first region and the second region; forming a first work function metal layer on the first BBM layer on the first region and the second region; removing the first work function metal (WFM) layer and part of the first BBM layer on the second region; and forming a diffusion barrier layer on the first WFM layer on the first region and the first BBM layer on the second region.

公开(公告)号：US20170373191A1

公开(公告)日：2017-12-28

申请号：US15214429

申请日：2016-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Chen Chan ,  Yi-Fan Li ,  Li-Wei Feng ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/0217 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. First, a fin-shaped structure is formed on a substrate, a first liner is formed on the substrate and the fin-shaped structure, a second liner is formed on the first liner, part of the second liner and part of the first liner are removed to expose a top surface of the fin-shaped structure, part of the first liner between the fin-shaped structure and the second liner is removed to form a recess, and an epitaxial layer is formed in the recess.