公开(公告)号：US11042485B2

公开(公告)日：2021-06-22

申请号：US16013263

申请日：2018-06-20

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Alexander Fainkichen ,  Ye Li ,  Regis Duchesne

IPC: G06F12/10 ,  G06F9/455

Abstract: An example method of implementing firmware runtime services in a computer system having a processor with a plurality of hierarchical privilege levels, the method including: calling, from software executing at a first privilege level of the processor, a runtime service stub in a firmware of the computer system; executing, by the runtime service stub, an upcall instruction from the first privilege level to a second privilege level of the processor that is more privileged than the first privilege level; and executing, by a handler, a runtime service at the second privilege level in response to execution of the upcall instruction.

公开(公告)号：US20190213033A1

公开(公告)日：2019-07-11

申请号：US16355497

申请日：2019-03-15

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Ye Li ,  Alexander Fainkichen

IPC: G06F9/455 ,  G06F9/50 ,  G06F1/3287 ,  G06F11/34 ,  G06F1/3234

CPC classification number: G06F9/45558 ,  G06F1/3234 ,  G06F1/3287 ,  G06F9/5077 ,  G06F11/3423

Abstract: Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.

公开(公告)号：US10331556B2

公开(公告)日：2019-06-25

申请号：US14838541

申请日：2015-08-28

Applicant: VMware, Inc.

Inventor： Cyprien Laplace ,  Harvey Tuch ,  Andrei Warkentin ,  Adrian Drzewiecki

IPC: G06F12/02 ,  G06F12/06 ,  G06F12/04 ,  G06F9/455

Abstract: A computer system provides a mechanism for assuring a safe, non-preemptible access to a private data area (PRDA) belonging to a CPU. PRDA accesses generally include obtaining an address of a PRDA and performing operations on the PRDA using the obtained address. Safe, non-preemptible access to a PRDA generally ensures that a context accesses the PRDA of the CPU on which the context is executing, but not the PRDA of another CPU. While a context executes on a first CPU, the context obtains the address of the PRDA. After the context is migrated to a second CPU, the context performs one or more operations on the PRDA belonging to the second CPU using the address obtained while the context executed on the first CPU. In another embodiment, preemption and possible migration of a context from one CPU to another CPU is delayed while a context executes non-preemptible code.

公开(公告)号：US12118362B2

公开(公告)日：2024-10-15

申请号：US17559346

申请日：2021-12-22

Applicant: VMware, Inc.

Inventor： Cyprien Laplace ,  Sunil Kumar Kotian ,  Andrei Warkentin ,  Regis Duchesne ,  Alexander Fainkichen ,  Shruthi Muralidhara Hiriyuru ,  Ye Li

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/455

CPC classification number: G06F9/3861 ,  G06F9/45558

Abstract: An example method of exception handling in a computer system is described. The computer system includes a physical central processing unit (PCPU) and a system memory, the system memory storing a first stack, a second stack, and a double fault stack associated with the PCPU. The method includes: storing, by an exception handler executing in the computer system, an exception frame on the double fault stack in response to a stack overflow condition of the first stack; switching, by the exception handler, a first stack pointer of the PCPU from pointing to the first stack to pointing to the double fault stack; setting a current stack pointer of the PCPU to the first stack pointer; and executing software on the PCPU with the current stack pointer pointing to the double fault stack.

公开(公告)号：US20230229480A1

公开(公告)日：2023-07-20

申请号：US17704040

申请日：2022-03-25

Applicant: VMWARE, INC.

Inventor： Andrei Warkentin ,  Karthik Ramachandra ,  Timothy P. Mann ,  Jared McNeill ,  Sunil Kotian ,  Cyprien Laplace ,  David A. Dunn

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45595

Abstract: Disclosed are various examples of provisioning a data processing unit (DPU) management operating system using a capsule. A management hypervisor installer executed on a host device receives a listing DPU device from a baseboard management controller (BMC). A preinstalled DPU management operating system image is identified for a DPU device from the listing, and is wrapped with a capsule that specifies the capsule as a DPU management operating system image capsule. A server component provides the DPU management operating system image capsule at a particular URI, and the URI is transmitted to the BMC.

公开(公告)号：US11561894B2

公开(公告)日：2023-01-24

申请号：US17142980

申请日：2021-01-06

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Alexander Fainkichen ,  Ye Li ,  Regis Duchesne ,  Cyprien Laplace ,  Shruthi Hiriyuru ,  Sunil Kotian

IPC: G06F12/06 ,  G06F9/455 ,  G06F13/16 ,  G06F13/42

Abstract: Techniques for enabling efficient guest OS access to PCIe configuration space are provided. In one set of embodiments, a hypervisor can reserve a single host physical memory page in the host physical memory of a host system and can populate the single host physical memory page with a value indicating non-presence of PCIe device functions. The hypervisor can then create, for each guest physical memory page in a guest physical memory of a virtual machine (VM) corresponding to a PCIe configuration space of an absent PCIe device function in the VM, a mapping in the hypervisor's second-level page tables that maps the guest physical memory page to the single host physical memory page.

公开(公告)号：US11113071B1

公开(公告)日：2021-09-07

申请号：US16935903

申请日：2020-07-22

Applicant: VMware, Inc.

Inventor： Cyprien Laplace ,  Andrei Warkentin ,  Shruthi Muralidhara Hiriyuru ,  Ye Li ,  Alexander Fainkichen ,  Regis Duchesne ,  Sunil Kumar Kotian ,  Renaud Benjamin Voltz

IPC: G06F9/44 ,  G06F9/4401 ,  G06F8/61

Abstract: A method for booting a computer system includes: loading a first stage bootloader of a plurality of first stage bootloaders from a boot image based on a known configuration of the computer system; executing the first stage bootloader to identify a selected bootbank of a plurality of bootbanks in the boot image based on the known configuration of the computer system; executing, by the first stage bootloader, a second stage bootloader from the boot image with an instruction to boot from the selected bootbank; and executing, by the second stage bootloader, a binary file in the selected bootbank.

公开(公告)号：US10922253B1

公开(公告)日：2021-02-16

申请号：US16660337

申请日：2019-10-22

Applicant: VMware, Inc.

Inventor： Regis Duchesne ,  Alexander Fainkichen ,  Cyprien Laplace ,  Ye Li ,  Andrei Warkentin

IPC: G06F13/24 ,  G06F13/16 ,  G06F13/10

Abstract: Disclosed are various embodiments for software-based interrupt remapping. A memory address for a respective interrupt request of the peripheral device is allocated. The peripheral device is then configured to write to the memory address to raise an interrupt with the processor. Later, it can be determined that the peripheral device has attempted to write to the memory address. In response, an interrupt can be raised for the respective interrupt request with the processor of the computing device on behalf of the peripheral device.

公开(公告)号：US10853284B1

公开(公告)日：2020-12-01

申请号：US16518818

申请日：2019-07-22

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Ye Li ,  Alexander Fainkichen ,  Cyprien Laplace

IPC: G06F13/26 ,  G06F13/42

Abstract: A method of handling message signaled interrupts in a computer system that uses an internal bus for communication between peripheral devices, using shared peripheral interrupt (SPI) vectors. The method includes determining whether a message signaled interrupt (MSI) needs to be allocated for a PCI-e device for an interrupt to be sent to a host. If it is determined that MSI needs to be allocated for the PCI-e device, a determination is made as to whether a Locality Specific Interrupt (LPI) register or an Interrupt Translation Service (ITS) is available to process the interrupt. If it is determined that neither the LPI register nor the Interrupt Translation Service (ITS) is available to process the interrupt, the PCI-e device is configured for SPI-based MSI generation to route the interrupt by determining an available SPI vector and assigning the available SPI vector to the PCI-e device.

公开(公告)号：US10795813B2

公开(公告)日：2020-10-06

申请号：US16420549

申请日：2019-05-23

Applicant: VMware, Inc.

Inventor： Cyprien Laplace ,  Harvey Tuch ,  Andrei Warkentin ,  Adrian Drzewiecki

IPC: G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F9/455

Abstract: A computer system provides a mechanism for assuring a safe, non-preemptible access to a private data area (PRDA) belonging to a CPU. PRDA accesses generally include obtaining an address of a PRDA and performing operations on the PRDA using the obtained address. Safe, non-preemptible access to a PRDA generally ensures that a context accesses the PRDA of the CPU on which the context is executing, but not the PRDA of another CPU. While a context executes on a first CPU, the context obtains the address of the PRDA. After the context is migrated to a second CPU, the context performs one or more operations on the PRDA belonging to the second CPU using the address obtained while the context executed on the first CPU. In another embodiment, preemption and possible migration of a context from one CPU to another CPU is delayed while a context executes non-preemptible code.