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    Method for switching address spaces via an intermediate address space
    21.
    发明授权
    Method for switching address spaces via an intermediate address space 有权

    公开(公告)号：US10185664B1

    公开(公告)日：2019-01-22

    申请号：US15639800

    申请日：2017-06-30

    Applicant: VMware, Inc.

    Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Alexander Fainkichen ,  Ye Li

    IPC: G06F9/4401 ,  G06F12/1027 ,  G06F12/1009 ,  G06F9/445

    Abstract: A method of re-mapping a boot loader image from a first to a second address space includes: determining a difference in a virtual address of the boot loader image in the first and second address spaces; building page tables for a third address space that maps a code section within the boot loader image at first and second address ranges separated by the difference and the code section causes execution to jump from a first instruction in the first address range to a second instruction in the second address range; executing an instruction of the code section in the first address space using pages tables for the first address space; executing the first instruction and then the second instruction using the page tables for the third address space; and executing an instruction of the boot loader image in the second address space using page tables for the second address space.

    DEVICE TREE RUNTIME MECHANISM
    22.
    发明公开
    DEVICE TREE RUNTIME MECHANISM 审中-公开

    公开(公告)号：US20240256286A1

    公开(公告)日：2024-08-01

    申请号：US18102379

    申请日：2023-01-27

    Applicant: VMware, Inc.

    Inventor： Andrei Warkentin ,  Regis Duchesne ,  Renukanthan Raman

    IPC: G06F9/4401

    CPC classification number: G06F9/4401

    Abstract: Systems and methods are included for causing a computing device to boot by retrieving hardware information from a device tree and further properties by utilizing a native access method call identified in the device tree. The access method can allow for getting a property, getting a property length, or setting a property. A table within firmware can identify the method, which then can retrieve the property information from memory. This Device tree Runtime (“DTRT”) mechanism can allow the computing device to retrieve the hardware configuration and act as a power management interface for turning on the correct hardware and hardware properties on the computing device.

    POWER EFFICIENT MEMORY VALUE UPDATES FOR ARM ARCHITECTURES
    24.
    发明公开
    POWER EFFICIENT MEMORY VALUE UPDATES FOR ARM ARCHITECTURES 审中-公开

    公开(公告)号：US20230237010A1

    公开(公告)日：2023-07-27

    申请号：US17580866

    申请日：2022-01-21

    Applicant: VMware, Inc.

    Inventor： Regis Duchesne ,  Andrei Warkentin ,  Cyprien Laplace ,  Ye Li ,  Alexander Fainkichen ,  Shruthi Hiriyuru ,  Sunil Kotian

    IPC: G06F15/78 ,  G06F9/30

    CPC classification number: G06F15/7842 ,  G06F9/30123

    Abstract: Disclosed are various examples of providing provide efficient waiting for detection of memory value updates for Advanced RISC Machines (ARM) architectures. An ARM processor component instructs a memory agent to perform a processing action, and executes a waiting function. The waiting function ensures that the processing action is completed by the memory agent. The waiting function performs an exclusive load at a memory location, and a wait for event (WFE) instruction that causes the ARM processor component to wait in a low-power mode for an event register to be set. Once the event register is set, the waiting function completes and a second processing action is executed by the ARM processor component.

    Non-unified cache coherency maintenance for virtual machines
    27.
    发明授权
    Non-unified cache coherency maintenance for virtual machines 有权

    公开(公告)号：US11210222B2

    公开(公告)日：2021-12-28

    申请号：US15878062

    申请日：2018-01-23

    Applicant: VMware, Inc.

    Inventor： Ye Li ,  Cyprien Laplace ,  Andrei Warkentin ,  Alexander Fainkichen ,  Regis Duchesne

    IPC: G06F12/0815 ,  G06F12/0808

    Abstract: An example method of maintaining cache coherency in a virtualized computing system includes: trapping access to a memory page by guest software in a virtual machine at a hypervisor managing the virtual machine, where the memory page is not mapped in a second stage page table managed by the hypervisor; performing cache coherency maintenance for instruction and data caches of a central processing unit (CPU) in the virtualized computing system in response to the trap; mapping the memory page in the second stage page table with execute permission; and resuming execution of the virtual machine.

    Implementing firmware runtime services in a computer system
    29.
    发明授权
    Implementing firmware runtime services in a computer system 有权

    公开(公告)号：US11042485B2

    公开(公告)日：2021-06-22

    申请号：US16013263

    申请日：2018-06-20

    Applicant: VMware, Inc.

    Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Alexander Fainkichen ,  Ye Li ,  Regis Duchesne

    IPC: G06F12/10 ,  G06F9/455

    Abstract: An example method of implementing firmware runtime services in a computer system having a processor with a plurality of hierarchical privilege levels, the method including: calling, from software executing at a first privilege level of the processor, a runtime service stub in a firmware of the computer system; executing, by the runtime service stub, an upcall instruction from the first privilege level to a second privilege level of the processor that is more privileged than the first privilege level; and executing, by a handler, a runtime service at the second privilege level in response to execution of the upcall instruction.

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