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    Dual-gate resurf superjunction lateral DMOSFET
    21.
    发明授权
    Dual-gate resurf superjunction lateral DMOSFET 失效
    双栅极复合超导型DMOSFET

    公开(公告)号：US06528849B1

    公开(公告)日：2003-03-04

    申请号：US09652813

    申请日：2000-08-31

    申请人： Vishnu K. Khemka ,  Vijay Parthasarathy ,  Ronghua Zhu ,  Amitava Bose

    发明人： Vishnu K. Khemka ,  Vijay Parthasarathy ,  Ronghua Zhu ,  Amitava Bose

    IPC分类号： H01L2978

    CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/7393 ,  H01L29/7831

    摘要： A MOSFET includes a source region, a first channel region proximate to the source region, a first gate region adjacent to the first base region, a drain region, a second channel region proximate to the drain region, and a second gate region adjacent to the second channel region. A first channel is formed within the first channel region in dependence upon a first voltage applied to the first gate region with respect to at least a first portion of the source region, and a second channel is formed within the second channel region in dependence upon a second voltage applied to the second gate region with respect to at least a second portion of the drain region. The MOSFET further includes a drift region coupled between the first channel region and the second channel region, where the drift region includes a set of alternating columns, each of which is also coupled between the first base region and the second base region. The set of alternating columns includes a plurality of columns doped with N− type impurities alternating with a plurality columns doped with P− type impurities.

    摘要翻译： MOSFET包括源极区域，靠近源极区域的第一沟道区域，与第一基极区域相邻的第一栅极区域，漏极区域，靠近漏极区域的第二沟道区域以及与漏极区域相邻的第二栅极区域 第二通道区域。 根据相对于源区域的至少第一部分施加到第一栅极区域的第一电压，在第一沟道区域内形成第一沟道，并且第二沟道形成在第二沟道区内，依赖于 相对于漏极区域的至少第二部分施加到第二栅极区域的第二电压。 MOSFET还包括耦合在第一沟道区域和第二沟道区域之间的漂移区域，其中漂移区域包括一组交替的列，其中每一个也耦合在第一基极区域和第二基极区域之间。 这组交替的列包括掺杂有多个掺杂有P-型杂质的列的N型杂质的多个列。

    Schottky device and method of forming
    22.
    发明授权
    Schottky device and method of forming 有权
    肖特基器件和成型方法

    公开(公告)号：US07355260B2

    公开(公告)日：2008-04-08

    申请号：US10881678

    申请日：2004-06-30

    申请人： Vishnu K. Khemka ,  Vijay Parthasarathy ,  Ronghua Zhu ,  Amitava Bose

    发明人： Vishnu K. Khemka ,  Vijay Parthasarathy ,  Ronghua Zhu ,  Amitava Bose

    IPC分类号： H01L27/095 ,  H01L29/47

    CPC分类号： H01L29/66143 ,  H01L29/812 ,  H01L29/872

    摘要： A conductive layer includes a first portion that forms a Schottky region with an underlying first region having a first conductivity type. A second region of a second conductivity type underlies the first region, where the second conductivity type is opposite the first conductivity type. A third region of the first conductivity type immediately underlies the second region and is electrically coupled to a cathode of the device.

    摘要翻译： 导电层包括形成具有第一导电类型的下面的第一区域的肖特基区域的第一部分。 第二导电类型的第二区域位于第一区域的正下方，其中第二导电类型与第一导电类型相反。 第一导电类型的第三区域刚好在第二区域的下面，并且电耦合到器件的阴极。

    LDMOS transistor
    23.
    发明授权
    LDMOS transistor 有权
    LDMOS晶体管

    公开(公告)号：US07141860B2

    公开(公告)日：2006-11-28

    申请号：US10875105

    申请日：2004-06-23

    申请人： Vishnu K. Khemka ,  Vijay Parthasarathy ,  Ronghua Zhu ,  Amitava Bose

    发明人： Vishnu K. Khemka ,  Vijay Parthasarathy ,  Ronghua Zhu ,  Amitava Bose

    IPC分类号： H01L27/95 ,  H01L29/47

    CPC分类号： H01L29/782 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/47 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

    摘要： An LDMOS transistor has a Schottky diode inserted at the center of a doped region of the LDMOS transistor. A Typical LDMOS transistor has a drift region in the center. In this case a Schottky diode is inserted at the center of this drift region which has the effect of providing a Schottky diode connected from source to drain in the forward direction so that the drain voltage is clamped to a voltage that is lower than the PN junction threshold, thereby avoiding forward biasing the PN junction. An alternative is to insert the Schottky diode at the well in which the source is formed, which is on the periphery of the LDMOS transistor. In such case the Schottky diode is formed differently but still is connected from source to drain in the forward direction to achieve the desired voltage clamping at the drain.

    摘要翻译： LDMOS晶体管具有插入在LDMOS晶体管的掺杂区域的中心处的肖特基二极管。 典型的LDMOS晶体管在中心具有漂移区域。 在这种情况下，肖特基二极管被插入该漂移区的中心，其具有在正向上提供从源极到漏极连接的肖特基二极管的作用，使得漏极电压被钳位到低于PN结的电压 阈值，从而避免正向偏置PN结。 一种替代方案是将肖特基二极管插入其中形成源的阱，其位于LDMOS晶体管的外围。 在这种情况下，肖特基二极管的形成方式不同，但仍然在正向方向上从源极到漏极连接，以在漏极处实现所需的电压钳位。

    Schottky device
    24.
    发明授权
    Schottky device 失效
    肖特基装置

    公开(公告)号：US07071518B2

    公开(公告)日：2006-07-04

    申请号：US10856602

    申请日：2004-05-28

    申请人： Vijay Parthasarathy ,  Vishnu K. Khemka ,  Ronghua Zhu ,  Amitava Bose

    发明人： Vijay Parthasarathy ,  Vishnu K. Khemka ,  Ronghua Zhu ,  Amitava Bose

    IPC分类号： H01L27/772

    CPC分类号： H01L27/0727 ,  H01L27/0629

    摘要： A regular Schottky diode or a device that has a Schottky diode characteristic and an MOS transistor are coupled in series to provide a significant improvement in leakage current and breakdown voltage with only a small degradation in forward current. In the reverse bias case, there is a small reverse bias current but the voltage across the Schottky diode remains small due the MOS transistor. Nearly all of the reverse bias voltage is across the MOS transistor until the MOS transistor breaks down. This transistor breakdown, however, is not initially destructive because the Schottky diode limits the current. As the reverse bias voltage continues to increase the Schottky diodes begins to absorb more of the voltage. This increases the leakage current but the breakdown voltage is a somewhat additive between the transistor and the Schottky diode.

    摘要翻译： 正交肖特基二极管或具有肖特基二极管特性和MOS晶体管的器件串联耦合以提供泄漏电流和击穿电压的显着改进，只有正​​向电流的降低很小。 在反向偏置情况下，存在小的反向偏置电流，但由于MOS晶体管，肖特基二极管两端的电压保持较小。 几乎所有的反向偏置电压都跨越MOS晶体管，直到MOS晶体管故障。 然而，该晶体管击穿不是最初的破坏性，因为肖特基二极管限制了电流。 随着反向偏压持续增加，肖特基二极管开始吸收更多的电压。 这增加了漏电流，但是在晶体管和肖特基二极管之间的击穿电压稍微相加。

    High-voltage monolithic schottky device structure
    27.
    发明授权
    High-voltage monolithic schottky device structure 有权
    高压单片肖特基器件结构

    公开(公告)号：US08653600B2

    公开(公告)日：2014-02-18

    申请号：US13487025

    申请日：2012-06-01

    申请人： Vijay Parthasarathy

    发明人： Vijay Parthasarathy

    IPC分类号： H01L29/66

    CPC分类号： H01L29/8725 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/36 ,  H01L29/407

    摘要： A semiconductor device includes a pillar formed on a substrate of the same conductivity type. The pillar has a vertical thickness that extends from a top surface down to the substrate. The pillar extends in first and second lateral directions in a loop shape. First and second dielectric regions are disposed on opposite lateral sides of the pillar, respectively. First and second conductive field plates are respectively disposed in the first and second dielectric regions. A metal layer is disposed on the top surface of the pillar, the metal layer forming a Schottky diode with respect to the pillar. When the substrate is raised to a high-voltage potential with respect to both the metal layer and the first and second field plates, the first and second field plates functioning capacitively to deplete the pillar of charge, thereby supporting the high-voltage potential along the vertical thickness of the pillar.

    摘要翻译： 半导体器件包括形成在相同导电类型的衬底上的柱。 该柱具有从顶部表面向下延伸到基底的垂直厚度。 支柱以第一和第二横向方向呈环形延伸。 第一和第二电介质区域分别设置在柱的相对侧面上。 第一和第二导电场板分别设置在第一和第二电介质区域中。 金属层设置在柱的顶表面上，金属层相对于柱形成肖特基二极管。 当基板相对于金属层和第一和第二场板两者升高到高压电位时，第一和第二场板电容地起作用以耗尽柱的电荷，从而支持沿着 柱的垂直厚度。

    High-Voltage Transistor Structure with Reduced Gate Capacitance
    28.
    发明申请
    High-Voltage Transistor Structure with Reduced Gate Capacitance 有权
    具有降低栅极电容的高压晶体管结构

    公开(公告)号：US20120273885A1

    公开(公告)日：2012-11-01

    申请号：US13532583

    申请日：2012-06-25

    申请人： Sujit Banerjee ,  Vijay Parthasarathy

    发明人： Sujit Banerjee ,  Vijay Parthasarathy

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7835 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0882 ,  H01L29/42368

    摘要： In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.

    摘要翻译： 在一个实施例中，高电压场效应晶体管（HVFET）包括覆盖第一阱区的场氧化物层，所述场氧化物层具有第一厚度并且在第二横向方向上从漏极区延伸到接近第二阱 地区。 栅极氧化物覆盖沟道区域并且具有在第一横向方向上的第二尺寸。 栅极在第二横向方向上从源极区域延伸到场氧化物层的一部分，栅极通过栅极氧化物与沟道区域绝缘，栅极在第一横向尺寸上延伸超过HVFET的非有效区域 超过栅极氧化物的第二维度，栅极通过场氧化物层与无源区域上的第一和第二阱区绝缘。

    High-voltage transistor device with integrated resistor
    29.
    发明申请
    High-voltage transistor device with integrated resistor 有权
    具有集成电阻的高压晶体管器件

    公开(公告)号：US20120146105A1

    公开(公告)日：2012-06-14

    申请号：US13385264

    申请日：2012-02-10

    申请人： Sujit Banerjee ,  Vijay Parthasarathy

    发明人： Sujit Banerjee ,  Vijay Parthasarathy

    IPC分类号： H01L27/06

    CPC分类号： H01L29/808 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0634 ,  H01L29/1058 ,  H01L29/1066

    摘要： A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

    摘要翻译： 高压器件结构包括耦合到抽头晶体管的电阻器，其包括JFET，其中当外部电压小于钳位电压时，在JFET的端子处提供的电压基本上与外部电压成比例 的JFET。 当外部电压大于夹断电压时，端子处提供的电压基本上恒定。 当外部电压大于夹断电压时，电阻器的一端基本上处于外部电压。 当外部电压为负时，电阻限制注入基板的电流。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。

    Checkerboarded high-voltage vertical transistor layout
    30.
    发明申请
    Checkerboarded high-voltage vertical transistor layout 失效
    棋盘式高压立式晶体管布局

    公开(公告)号：US20120061755A1

    公开(公告)日：2012-03-15

    申请号：US13199792

    申请日：2011-09-09

    申请人： Vijay Parthasarathy ,  Sujit Banerjee ,  Martin H. Manley

    发明人： Vijay Parthasarathy ,  Sujit Banerjee ,  Martin H. Manley

    IPC分类号： H01L29/78

    CPC分类号： H01L27/0211 ,  H01L27/0207 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7813

    摘要： In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.

    摘要翻译： 在一个实施例中，制造在半导体管芯上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分和设置在邻近第一区域的半导体管芯的第二区域中的晶体管段的第二部分。 第一和第二部分中的每个晶体管段包括在垂直方向上延伸的半导体材料的柱。 第一和第二电介质区域设置在柱的相对侧上。 第一和第二场板分别设置在第一和第二电介质区域中。 邻接第一和第二部分的晶体管段的外场板被分离或部分合并。