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    VISUALIZATION OF CATHETER OF THREE-DIMENSIONAL ULTRASOUND
    2.
    发明申请
    VISUALIZATION OF CATHETER OF THREE-DIMENSIONAL ULTRASOUND 有权
    三维超声波导管的可视化

    公开(公告)号：US20130281839A1

    公开(公告)日：2013-10-24

    申请号：US13997800

    申请日：2012-01-10

    申请人： Pingkun Yan ,  Vijay Parthasarathy ,  Robert Manzke ,  Ameet Kumar Jain

    发明人： Pingkun Yan ,  Vijay Parthasarathy ,  Robert Manzke ,  Ameet Kumar Jain

    IPC分类号： A61B19/00

    CPC分类号： A61B34/20 ,  A61B6/12 ,  A61B8/0883 ,  A61B8/466 ,  A61B8/483

    摘要： An image-guided system employs an X-ray imaging device (20) for generating one or more X-ray images (25, 26) illustrating a tool (41) within an anatomical region (40) and an ultrasound imaging device (30) for generating an ultrasound image (33) illustrating the tool (41) within the anatomical region (40). The image-guided system further employs a tool tracking device (50) for visually tracking the tool (41) within the anatomical region (40). In operation, the tool tracking device (50) localizes a portion of the tool (41) as located within the ultrasound image (33) responsive to an identification of the portion of the tool (41) as located within the X-ray image(s) (25, 26), and executes an image segmentation of an entirety of the tool (41) as located within the ultrasound image (33) relative to a localization of the portion of the tool (41) as located within the ultrasound image (33).

    摘要翻译： 图像引导系统采用X射线成像装置（20），用于产生示出解剖区域（40）内的工具（41）和超声成像装置（30）的一个或多个X射线图像（25,26） 用于产生示出所述解剖区域（40）内的所述工具（41）的超声图像（33）。 图像引导系统还采用用于在解剖区域（40）内目视跟踪工具（41）的工具跟踪装置（50）。 在操作中，工具跟踪装置（50）响应于位于X射线图像内的工具（41）的部分的识别，使位于超声波图像（33）内的工具（41）的一部分定位 s）（25,26），并且相对于位于超声波图像内的工具（41）的部分的定位，执行位于超声波图像（33）内的整个工具（41）的图像分割 （33）。

    High-voltage monolithic schottky device structure
    6.
    发明授权
    High-voltage monolithic schottky device structure 有权
    高压单片肖特基器件结构

    公开(公告)号：US08653600B2

    公开(公告)日：2014-02-18

    申请号：US13487025

    申请日：2012-06-01

    申请人： Vijay Parthasarathy

    发明人： Vijay Parthasarathy

    IPC分类号： H01L29/66

    CPC分类号： H01L29/8725 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/36 ,  H01L29/407

    摘要： A semiconductor device includes a pillar formed on a substrate of the same conductivity type. The pillar has a vertical thickness that extends from a top surface down to the substrate. The pillar extends in first and second lateral directions in a loop shape. First and second dielectric regions are disposed on opposite lateral sides of the pillar, respectively. First and second conductive field plates are respectively disposed in the first and second dielectric regions. A metal layer is disposed on the top surface of the pillar, the metal layer forming a Schottky diode with respect to the pillar. When the substrate is raised to a high-voltage potential with respect to both the metal layer and the first and second field plates, the first and second field plates functioning capacitively to deplete the pillar of charge, thereby supporting the high-voltage potential along the vertical thickness of the pillar.

    摘要翻译： 半导体器件包括形成在相同导电类型的衬底上的柱。 该柱具有从顶部表面向下延伸到基底的垂直厚度。 支柱以第一和第二横向方向呈环形延伸。 第一和第二电介质区域分别设置在柱的相对侧面上。 第一和第二导电场板分别设置在第一和第二电介质区域中。 金属层设置在柱的顶表面上，金属层相对于柱形成肖特基二极管。 当基板相对于金属层和第一和第二场板两者升高到高压电位时，第一和第二场板电容地起作用以耗尽柱的电荷，从而支持沿着 柱的垂直厚度。

    High-Voltage Transistor Structure with Reduced Gate Capacitance
    7.
    发明申请
    High-Voltage Transistor Structure with Reduced Gate Capacitance 有权
    具有降低栅极电容的高压晶体管结构

    公开(公告)号：US20120273885A1

    公开(公告)日：2012-11-01

    申请号：US13532583

    申请日：2012-06-25

    申请人： Sujit Banerjee ,  Vijay Parthasarathy

    发明人： Sujit Banerjee ,  Vijay Parthasarathy

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7835 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0882 ,  H01L29/42368

    摘要： In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.

    摘要翻译： 在一个实施例中，高电压场效应晶体管（HVFET）包括覆盖第一阱区的场氧化物层，所述场氧化物层具有第一厚度并且在第二横向方向上从漏极区延伸到接近第二阱 地区。 栅极氧化物覆盖沟道区域并且具有在第一横向方向上的第二尺寸。 栅极在第二横向方向上从源极区域延伸到场氧化物层的一部分，栅极通过栅极氧化物与沟道区域绝缘，栅极在第一横向尺寸上延伸超过HVFET的非有效区域 超过栅极氧化物的第二维度，栅极通过场氧化物层与无源区域上的第一和第二阱区绝缘。

    High-voltage transistor device with integrated resistor
    8.
    发明申请
    High-voltage transistor device with integrated resistor 有权
    具有集成电阻的高压晶体管器件

    公开(公告)号：US20120146105A1

    公开(公告)日：2012-06-14

    申请号：US13385264

    申请日：2012-02-10

    申请人： Sujit Banerjee ,  Vijay Parthasarathy

    发明人： Sujit Banerjee ,  Vijay Parthasarathy

    IPC分类号： H01L27/06

    CPC分类号： H01L29/808 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0634 ,  H01L29/1058 ,  H01L29/1066

    摘要： A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

    摘要翻译： 高压器件结构包括耦合到抽头晶体管的电阻器，其包括JFET，其中当外部电压小于钳位电压时，在JFET的端子处提供的电压基本上与外部电压成比例 的JFET。 当外部电压大于夹断电压时，端子处提供的电压基本上恒定。 当外部电压大于夹断电压时，电阻器的一端基本上处于外部电压。 当外部电压为负时，电阻限制注入基板的电流。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。

    Checkerboarded high-voltage vertical transistor layout
    9.
    发明申请
    Checkerboarded high-voltage vertical transistor layout 失效
    棋盘式高压立式晶体管布局

    公开(公告)号：US20120061755A1

    公开(公告)日：2012-03-15

    申请号：US13199792

    申请日：2011-09-09

    申请人： Vijay Parthasarathy ,  Sujit Banerjee ,  Martin H. Manley

    发明人： Vijay Parthasarathy ,  Sujit Banerjee ,  Martin H. Manley

    IPC分类号： H01L29/78

    CPC分类号： H01L27/0211 ,  H01L27/0207 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7813

    摘要： In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.

    摘要翻译： 在一个实施例中，制造在半导体管芯上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分和设置在邻近第一区域的半导体管芯的第二区域中的晶体管段的第二部分。 第一和第二部分中的每个晶体管段包括在垂直方向上延伸的半导体材料的柱。 第一和第二电介质区域设置在柱的相对侧上。 第一和第二场板分别设置在第一和第二电介质区域中。 邻接第一和第二部分的晶体管段的外场板被分离或部分合并。

    Method of fabricating a deep trench insulated gate bipolar transistor
    10.
    发明申请
    Method of fabricating a deep trench insulated gate bipolar transistor 失效

    公开(公告)号：US20110140166A1

    公开(公告)日：2011-06-16

    申请号：US12930626

    申请日：2011-01-11

    申请人： Vijay Parthasarathy ,  Sujit Banerjee

    发明人： Vijay Parthasarathy ,  Sujit Banerjee

    IPC分类号： H01L29/739

    CPC分类号： H01L29/7397 ,  H01L29/66333

    摘要： In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.