公开(公告)号：US20240233819A9

公开(公告)日：2024-07-11

申请号：US18399609

申请日：2023-12-28

Applicant: Winbond Electronics Corp.

Inventor： Ming-Che Lin ,  Min-Chih Wei ,  Ping-Kun Wang ,  Yu-Ting Chen ,  Chih-Cheng Fu ,  Chang-Tsung Pai

IPC: G11C13/00

CPC classification number: G11C13/0038 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/79

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

公开(公告)号：US20240135990A1

公开(公告)日：2024-04-25

申请号：US18399609

申请日：2023-12-28

Applicant: Winbond Electronics Corp.

Inventor： Ming-Che Lin ,  Min-Chih Wei ,  Ping-Kun Wang ,  Yu-Ting Chen ,  Chih-Cheng Fu ,  Chang-Tsung Pai

IPC: G11C13/00

CPC classification number: G11C13/0038 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/79

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

公开(公告)号：US11538525B2

公开(公告)日：2022-12-27

申请号：US17495778

申请日：2021-10-06

Applicant: Winbond Electronics Corp.

Inventor： Ping-Kun Wang ,  Ming-Che Lin ,  Yu-Ting Chen ,  Chang-Tsung Pai ,  Shao-Ching Liao ,  Chi-Ching Liu

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Provided is a resetting method of a resistive random access memory (RRAM) including the following steps. A first resetting operation and a first verifying operation on the at least one resistive memory cell are performed. Whether to perform a second resetting operation according to a verifying result of the first verifying operation is determined. A second verifying operation is performed after the second resetting operation is determined to be performed and is finished. To determine whether to perform a healing resetting operation according to a verifying result of the second verifying operation, which comprises: performing the healing resetting operation when a verifying current of the second verifying operation is greater than a predetermined current, wherein a resetting voltage of the healing resetting operation is greater than a resetting voltage of the second resetting operation.

公开(公告)号：US20210175418A1

公开(公告)日：2021-06-10

申请号：US16709863

申请日：2019-12-10

Applicant: Winbond Electronics Corp.

Inventor： Po-Yen Hsu ,  Bo-Lun Wu ,  Ping-Kun Wang ,  Ming-Che Lin ,  Yu-Ting Chen ,  Chang-Tsung Pai ,  Shao-Ching Liao ,  Chi-Ching Liu

IPC: H01L45/00

Abstract: A resistive random access memory including first and second electrodes, a resistance variable layer, first and second metal layers and a resistance stabilizing layer is provided. The second electrode is disposed on the first electrode. The resistance variable layer is disposed between the first and second electrodes. The first metal layer is disposed between the resistance variable layer and the second electrode. The second metal layer is disposed between the first metal layer and the second electrode. The resistance stabilizing layer is disposed between the first and second metal layers. The oxygen content of the resistance variable layer is higher than that of the first metal layer, the oxygen content of the first metal layer is higher than that of the resistance stabilizing layer, the oxygen content of the resistance stabilizing layer is higher than that of the second metal layer.