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    RESISTIVE MEMORY APPARATUS AND OPERATING METHOD THEREOF AND MEMORY CELL ARRAY THEREOF
    2.
    发明申请
    RESISTIVE MEMORY APPARATUS AND OPERATING METHOD THEREOF AND MEMORY CELL ARRAY THEREOF 有权

    公开(公告)号：US20220068382A1

    公开(公告)日：2022-03-03

    申请号：US17458559

    申请日：2021-08-27

    Applicant: Winbond Electronics Corp.

    Inventor： Ming-Che Lin ,  Min-Chih Wei ,  Ping-Kun Wang ,  Yu-Ting Chen ,  Chih-Cheng Fu ,  Chang-Tsung Pai

    IPC: G11C13/00

    Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210057640A1

    公开(公告)日：2021-02-25

    申请号：US16991055

    申请日：2020-08-12

    Applicant: Winbond Electronics Corp.

    Inventor： Wen-Chia Ou ,  Chih-Chao Huang ,  Min-Chih Wei ,  Yu-Ting Chen ,  Chi-Ching Liu

    IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

    Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250072295A1

    公开(公告)日：2025-02-27

    申请号：US18945580

    申请日：2024-11-13

    Applicant: Winbond Electronics Corp.

    Inventor： Wen-Chia Ou ,  Chih-Chao Huang ,  Min-Chih Wei ,  Yu-Ting Chen ,  Chi-Ching Liu

    IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

    Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.

    Semiconductor device and method of fabricating the same
    5.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US12193337B2

    公开(公告)日：2025-01-07

    申请号：US16991055

    申请日：2020-08-12

    Applicant: Winbond Electronics Corp.

    Inventor： Wen-Chia Ou ,  Chih-Chao Huang ,  Min-Chih Wei ,  Yu-Ting Chen ,  Chi-Ching Liu

    IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

    Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.

    RESISTIVE MEMORY APPARATUS AND OPERATING METHOD THEREOF AND MEMORY CELL ARRAY THEREOF
    7.
    发明公开
    RESISTIVE MEMORY APPARATUS AND OPERATING METHOD THEREOF AND MEMORY CELL ARRAY THEREOF 审中-公开

    公开(公告)号：US20240233819A9

    公开(公告)日：2024-07-11

    申请号：US18399609

    申请日：2023-12-28

    Applicant: Winbond Electronics Corp.

    Inventor： Ming-Che Lin ,  Min-Chih Wei ,  Ping-Kun Wang ,  Yu-Ting Chen ,  Chih-Cheng Fu ,  Chang-Tsung Pai

    IPC: G11C13/00

    CPC classification number: G11C13/0038 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/79

    Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

    RESISTIVE MEMORY APPARATUS AND OPERATING METHOD THEREOF AND MEMORY CELL ARRAY THEREOF
    8.
    发明公开
    RESISTIVE MEMORY APPARATUS AND OPERATING METHOD THEREOF AND MEMORY CELL ARRAY THEREOF 审中-公开

    公开(公告)号：US20240135990A1

    公开(公告)日：2024-04-25

    申请号：US18399609

    申请日：2023-12-28

    Applicant: Winbond Electronics Corp.

    Inventor： Ming-Che Lin ,  Min-Chih Wei ,  Ping-Kun Wang ,  Yu-Ting Chen ,  Chih-Cheng Fu ,  Chang-Tsung Pai

    IPC: G11C13/00

    CPC classification number: G11C13/0038 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/79

    Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

    Memory storage apparatus and forming method of resistive memory device
    9.
    发明授权
    Memory storage apparatus and forming method of resistive memory device 有权

    公开(公告)号：US10658036B2

    公开(公告)日：2020-05-19

    申请号：US16045749

    申请日：2018-07-26

    Applicant: Winbond Electronics Corp.

    Inventor： Shao-Ching Liao ,  Ping-Kun Wang ,  Ming-Che Lin ,  Min-Chih Wei ,  Chia-Hua Ho ,  Chien-Min Wu

    IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  G11C7/04

    Abstract: A forming method of a resistive memory device is provided. The forming method includes: conducting a forming procedure to apply a forming voltage to the resistive memory device such that the resistive memory device changes from a high resistive state to a low resistive state and measuring a first current of the resistive memory device; performing a thermal step on the resistive memory device and measuring a second current of the resistive memory device; and comparing the second current to the first current and determining to apply a first voltage signal or a second voltage signal to the resistive memory device or to finish the forming procedure according to a comparison result of the first current and the second current. In addition, a memory storage apparatus including a resistive memory device is also provided.

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