-
公开(公告)号：US11620500B2
公开(公告)日：2023-04-04
申请号：US15868392
申请日：2018-01-11
发明人： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Chih-Cheng Fu , Ming-Che Lin , Yu-Ting Chen , Seow-Fong (Dennis) Lim
摘要： A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.
-
公开(公告)号：US20240233819A9
公开(公告)日：2024-07-11
申请号：US18399609
申请日：2023-12-28
发明人： Ming-Che Lin , Min-Chih Wei , Ping-Kun Wang , Yu-Ting Chen , Chih-Cheng Fu , Chang-Tsung Pai
IPC分类号： G11C13/00
CPC分类号： G11C13/0038 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
-
公开(公告)号：US20240135990A1
公开(公告)日：2024-04-25
申请号：US18399609
申请日：2023-12-28
发明人： Ming-Che Lin , Min-Chih Wei , Ping-Kun Wang , Yu-Ting Chen , Chih-Cheng Fu , Chang-Tsung Pai
IPC分类号： G11C13/00
CPC分类号： G11C13/0038 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
-
公开(公告)号：US20170125673A1
公开(公告)日：2017-05-04
申请号：US15064603
申请日：2016-03-09
发明人： Po-Yen Hsu , Ting-Ying Shen , Chia-Hua Ho , Chih-Cheng Fu , Frederick Chen
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/124 , H01L45/1253 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： Provided are a resistive memory and a method of fabricating the resistive memory. The resistive memory includes a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protection layer. The first electrode and the second electrode are arranged opposite to each other. The variable resistance layer is arranged between the first electrode and the second electrode. The oxygen exchange layer is arranged between the variable resistance layer and the second electrode. The protection layer is arranged at least on sidewalls of the oxygen exchange layer.
-
公开(公告)号：US11908516B2
公开(公告)日：2024-02-20
申请号：US17458559
申请日：2021-08-27
发明人： Ming-Che Lin , Min-Chih Wei , Ping-Kun Wang , Yu-Ting Chen , Chih-Cheng Fu , Chang-Tsung Pai
CPC分类号： G11C13/0038 , G11C13/004 , G11C13/0026 , G11C13/0028 , G11C2213/79
摘要： A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
-
公开(公告)号：US11024802B2
公开(公告)日：2021-06-01
申请号：US16684547
申请日：2019-11-14
发明人： Po-Yen Hsu , Ting-Ying Shen , Chia-Hua Ho , Chih-Cheng Fu , Frederick Chen
IPC分类号： H01L45/00
摘要： Provided is a method of fabricating a resistive memory including forming a first electrode and a second electrode opposite to each other; forming a variable resistance layer between the first electrode and the second electrode; forming an oxygen exchange layer between the variable resistance layer and the second electrode; and forming a protection layer at least covering sidewalls of the oxygen exchange layer.
-
公开(公告)号：US20200083446A1
公开(公告)日：2020-03-12
申请号：US16684547
申请日：2019-11-14
发明人： Po-Yen Hsu , Ting-Ying Shen , Chia-Hua Ho , Chih-Cheng Fu , Frederick Chen
IPC分类号： H01L45/00
摘要： Provided is a method of fabricating a resistive memory including forming a first electrode and a second electrode opposite to each other; forming a variable resistance layer between the first electrode and the second electrode; forming an oxygen exchange layer between the variable resistance layer and the second electrode; and forming a protection layer at least covering sidewalls of the oxygen exchange layer.
-
公开(公告)号：US10522755B2
公开(公告)日：2019-12-31
申请号：US15064603
申请日：2016-03-09
发明人： Po-Yen Hsu , Ting-Ying Shen , Chia-Hua Ho , Chih-Cheng Fu , Frederick Chen
IPC分类号： H01L45/00
摘要： Provided are a resistive memory and a method of fabricating the resistive memory. The resistive memory includes a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protection layer. The first electrode and the second electrode are arranged opposite to each other. The variable resistance layer is arranged between the first electrode and the second electrode. The oxygen exchange layer is arranged between the variable resistance layer and the second electrode. The protection layer is arranged at least on sidewalls of the oxygen exchange layer.
-
公开(公告)号：US20220068382A1
公开(公告)日：2022-03-03
申请号：US17458559
申请日：2021-08-27
发明人： Ming-Che Lin , Min-Chih Wei , Ping-Kun Wang , Yu-Ting Chen , Chih-Cheng Fu , Chang-Tsung Pai
IPC分类号： G11C13/00
摘要： A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
-
公开(公告)号：US11107983B2
公开(公告)日：2021-08-31
申请号：US17060300
申请日：2020-10-01
发明人： Chih-Cheng Fu , Ming-Che Lin
摘要： A RRAM array and its manufacturing method are provided. The RRAM array includes a substrate having an array region which has a first region and a second region. The RRAM array includes a bottom electrode layer on the substrate, an oxygen ion reservoir layer on the bottom electrode layer, a diffusion barrier layer on the oxygen ion reservoir layer, a resistance switching layer on the diffusion barrier layer, and a top electrode layer on the resistance switching layer. The diffusion barrier layer in the first region is different from the diffusion barrier layer in the second region.
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.014 秒)
