公开(公告)号：US20220028454A1

公开(公告)日：2022-01-27

申请号：US17495778

申请日：2021-10-06

Applicant: Winbond Electronics Corp.

Inventor： Ping-Kun Wang ,  Ming-Che Lin ,  Yu-Ting Chen ,  Chang-Tsung Pai ,  Shao-Ching Liao ,  Chi-Ching Liu

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Provided is a resetting method of a resistive random access memory (RRAM) including the following steps. A first resetting operation and a first verifying operation on the at least one resistive memory cell are performed. Whether to perform a second resetting operation according to a verifying result of the first verifying operation is determined. A second verifying operation is performed after the second resetting operation is determined to be performed and is finished. To determine whether to perform a healing resetting operation according to a verifying result of the second verifying operation, which comprises: performing the healing resetting operation when a verifying current of the second verifying operation is greater than a predetermined current, wherein a resetting voltage of the healing resetting operation is greater than a resetting voltage of the second resetting operation.

公开(公告)号：US11055021B2

公开(公告)日：2021-07-06

申请号：US16353339

申请日：2019-03-14

Applicant: Winbond Electronics Corp.

Inventor： Ping-Kun Wang ,  Shao-Ching Liao ,  Chien-Min Wu ,  Chia Hua Ho ,  Frederick Chen ,  He-Hsuan Chao ,  Seow-Fong Lim

IPC: G06F3/06 ,  G06F11/07 ,  G11C13/00

Abstract: A resistive memory including a storage array, a storage circuit, a control circuit, a voltage generation circuit and an access circuit is provided. The storage array includes a plurality of blocks. Each block includes a plurality of memory cells. The storage circuit stores a plurality of count values. Each of the count values indicates the number of times that a corresponding block performs a write operation. The control circuit generates a control signal according to the count values when an external command is a write command. The voltage generation circuit provides an operation voltage group according to the control signal. The access circuit accesses the storage array according to the operation voltage group.

公开(公告)号：US20210012839A1

公开(公告)日：2021-01-14

申请号：US15930469

申请日：2020-05-13

Applicant: Winbond Electronics Corp.

Inventor： Ping-Kun Wang ,  Ming-Che Lin ,  Yu-Ting Chen ,  Chang-Tsung Pai ,  Shao-Ching Liao ,  Chi-Ching Liu

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer.

公开(公告)号：US20200350013A1

公开(公告)日：2020-11-05

申请号：US16726206

申请日：2019-12-23

Applicant: Winbond Electronics Corp.

Inventor： Shao-Ching Liao ,  Ping-Kun Wang

IPC: G11C13/00

Abstract: A resistive memory apparatus and an operating method thereof are provided. In the method, a set operation having a first enhanced bias is performed on at least one memory cell in a resistive memory array of the resistive memory apparatus, in which the first enhanced bias is larger than a bias used in a normal execution of the set operation. A heat process is performed on the memory cell. A set operation having a second enhanced bias is performed on the memory cell, in which the second enhanced bias is larger than or equal to the first enhanced bias.

公开(公告)号：US10770167B1

公开(公告)日：2020-09-08

申请号：US16281063

申请日：2019-02-20

Applicant: Winbond Electronics Corp.

Inventor： Ping-Kun Wang ,  Ming-Che Lin ,  Chien-Min Wu ,  He-Hsuan Chao ,  Chih-Cheng Fu ,  Shao-Ching Liao

IPC: G11C13/00 ,  G11C29/50 ,  G11C29/02 ,  G11C29/24

Abstract: A memory storage apparatus and a forming method of a resistive memory device thereof are provided. A test forming voltage is applied to a redundant resistive memory device and a corresponding test current is read. A forming voltage applied to a main memory cell block is determined according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.

公开(公告)号：US20200265914A1

公开(公告)日：2020-08-20

申请号：US16281063

申请日：2019-02-20

Applicant: Winbond Electronics Corp.

Inventor： Ping-Kun Wang ,  Ming-Che Lin ,  Chien-Min Wu ,  He-Hsuan Chao ,  Chih-Cheng Fu ,  Shao-Ching Liao

IPC: G11C29/50 ,  G11C13/00 ,  G11C29/24 ,  G11C29/02

Abstract: A memory storage apparatus and a forming method of a resistive memory device thereof are provided. A test forming voltage is applied to a redundant resistive memory device and a corresponding test current is read. A forming voltage applied to a main memory cell block is determined according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.

公开(公告)号：US20240282397A1

公开(公告)日：2024-08-22

申请号：US18171666

申请日：2023-02-21

Applicant: Winbond Electronics Corp.

Inventor： Shao-Ching Liao ,  Chien-Min Wu ,  Kuang-Chih Hsieh

IPC: G11C29/50

CPC classification number: G11C29/50 ,  G11C2029/5004

Abstract: A semiconductor memory apparatus and a testing method thereof are provided. The semiconductor memory apparatus includes a memory chip and a memory controller. The memory controller is configured to detect an initial test voltage of a target memory cell corresponding to a tailing bit in a main array of the memory chip. After the memory chip is idle for a first time, the memory controller detects a first test voltage of the target memory cell and compares it with a current comparison voltage to determine whether a first stage test is passed. In a case of passing the first stage test, after the memory chip is idle for a second time, the memory controller detects a second test voltage of the target memory cell and compares it with the current comparison voltage to determine whether a second stage test is passed. The comparison voltage is dynamically updated in response to the time the memory chip is idle.

公开(公告)号：US11152566B2

公开(公告)日：2021-10-19

申请号：US16709863

申请日：2019-12-10

Applicant: Winbond Electronics Corp.

Inventor： Po-Yen Hsu ,  Bo-Lun Wu ,  Ping-Kun Wang ,  Ming-Che Lin ,  Yu-Ting Chen ,  Chang-Tsung Pai ,  Shao-Ching Liao ,  Chi-Ching Liu

IPC: H01L45/00

Abstract: A resistive random access memory including first and second electrodes, a resistance variable layer, first and second metal layers and a resistance stabilizing layer is provided. The second electrode is disposed on the first electrode. The resistance variable layer is disposed between the first and second electrodes. The first metal layer is disposed between the resistance variable layer and the second electrode. The second metal layer is disposed between the first metal layer and the second electrode. The resistance stabilizing layer is disposed between the first and second metal layers. The oxygen content of the resistance variable layer is higher than that of the first metal layer, the oxygen content of the first metal layer is higher than that of the resistance stabilizing layer, the oxygen content of the resistance stabilizing layer is higher than that of the second metal layer.

公开(公告)号：US10593877B2

公开(公告)日：2020-03-17

申请号：US15949078

申请日：2018-04-10

Applicant: Winbond Electronics Corp.

Inventor： Frederick Chen ,  Ping-Kun Wang ,  Shao-Ching Liao ,  Po-Yen Hsu ,  Yi-Hsiu Chen ,  Ting-Ying Shen ,  Bo-Lun Wu ,  Meng-Hung Lin ,  Chia-Hua Ho ,  Ming-Che Lin

IPC: H01L45/00 ,  H01L27/24

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.

公开(公告)号：US20170170394A1

公开(公告)日：2017-06-15

申请号：US14967386

申请日：2015-12-14

Applicant: Winbond Electronics Corp.

Inventor： Frederick Chen ,  Ping-Kun Wang ,  Shao-Ching Liao ,  Po-Yen Hsu ,  Yi-Hsiu Chen ,  Ting-Ying Shen ,  Bo-Lun Wu ,  Meng-Hung Lin

IPC: H01L45/00

CPC classification number: H01L45/1266 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/146

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.