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公开(公告)号：US12063796B2
公开(公告)日：2024-08-13
申请号：US17960121
申请日：2022-10-04
Applicant: Winbond Electronics Corp.
Inventor： Chia-Wen Cheng , Ping-Kun Wang , Yi-Hsiu Chen , He-Hsuan Chao
CPC classification number: H10B63/84 , H10B63/30 , H10N70/061 , H10N70/841
Abstract: A manufacturing method is provided. The method includes steps below. Forming bottom electrodes. Blanketly forming a resistance switching layer on the bottom electrodes. Forming a first insulating material layer on the resistance switching layer. Patterning the first insulating material layer to form insulating patterns. Conformally forming a channel layer having a plurality of channel regions on the resistance switching layer and the insulating patterns, wherein the plurality of channel regions are located on the resistance switching layer and cover opposite sides of the insulating patterns. Forming a second electrode material layer on the channel layer. Patterning the second electrode material layer to form top electrodes, each of the top electrodes is located in corresponding to one of the insulating patterns and covers at least two of the plurality of channel regions.
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公开(公告)号：US11908516B2
公开(公告)日：2024-02-20
申请号：US17458559
申请日：2021-08-27
Applicant: Winbond Electronics Corp.
Inventor： Ming-Che Lin , Min-Chih Wei , Ping-Kun Wang , Yu-Ting Chen , Chih-Cheng Fu , Chang-Tsung Pai
CPC classification number: G11C13/0038 , G11C13/004 , G11C13/0026 , G11C13/0028 , G11C2213/79
Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
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公开(公告)号：US11502131B2
公开(公告)日：2022-11-15
申请号：US16952085
申请日：2020-11-19
Applicant: Winbond Electronics Corp.
Inventor： Chia-Wen Cheng , Ping-Kun Wang , Yi-Hsiu Chen , He-Hsuan Chao
Abstract: A resistive random access memory (RRAM) device and a manufacturing method are provided. The RRAM device includes bottom electrodes, a resistance switching layer, insulating patterns, a channel layer and top electrodes. The resistance switching layer blanketly covers the bottom electrodes. The insulating patterns are disposed on the resistance layer and located in corresponding to locations of the bottom electrodes. The channel layer conformally covers the resistance switching layer and the insulating patterns. The channel layer has a plurality of channel regions. The channel regions are located on the resistance switching layer, and cover sidewalls of the insulating patterns. The top electrodes respectively cover at least two of the channel regions, and respectively located in corresponding to one of the insulating patterns, such that the at least two of the channel regions are located between one of the bottom electrodes and one of the top electrodes.
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公开(公告)号：US11152566B2
公开(公告)日：2021-10-19
申请号：US16709863
申请日：2019-12-10
Applicant: Winbond Electronics Corp.
Inventor： Po-Yen Hsu , Bo-Lun Wu , Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
IPC: H01L45/00
Abstract: A resistive random access memory including first and second electrodes, a resistance variable layer, first and second metal layers and a resistance stabilizing layer is provided. The second electrode is disposed on the first electrode. The resistance variable layer is disposed between the first and second electrodes. The first metal layer is disposed between the resistance variable layer and the second electrode. The second metal layer is disposed between the first metal layer and the second electrode. The resistance stabilizing layer is disposed between the first and second metal layers. The oxygen content of the resistance variable layer is higher than that of the first metal layer, the oxygen content of the first metal layer is higher than that of the resistance stabilizing layer, the oxygen content of the resistance stabilizing layer is higher than that of the second metal layer.
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公开(公告)号：US10937495B2
公开(公告)日：2021-03-02
申请号：US16460995
申请日：2019-07-02
Applicant: Winbond Electronics Corp.
Inventor： He-Hsuan Chao , Ping-Kun Wang , Seow Fong Lim , Norio Hattori , Chien-Min Wu , Chih-Hua Hung
Abstract: A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.
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Patent Agency Ranking
公开(公告)号：US10593877B2
公开(公告)日：2020-03-17
申请号：US15949078
申请日：2018-04-10
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Po-Yen Hsu , Yi-Hsiu Chen , Ting-Ying Shen , Bo-Lun Wu , Meng-Hung Lin , Chia-Hua Ho , Ming-Che Lin
Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.
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公开(公告)号：US20170170394A1
公开(公告)日：2017-06-15
申请号：US14967386
申请日：2015-12-14
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Po-Yen Hsu , Yi-Hsiu Chen , Ting-Ying Shen , Bo-Lun Wu , Meng-Hung Lin
IPC: H01L45/00
CPC classification number: H01L45/1266 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/124 , H01L45/146
Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.
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公开(公告)号：US09443587B1
公开(公告)日：2016-09-13
申请号：US14804354
申请日：2015-07-21
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Meng-Hung Lin , Ping-Kun Wang , Shao-Ching Liao , Chuan-Sheng Chou
CPC classification number: G11C13/0069 , G11C13/0064 , G11C2013/0066 , G11C2013/0073 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092
Abstract: A resistive memory apparatus and a writing method thereof are provided. In the method, logic data is received, and a corresponding resistive memory cell is selected. A logic level of the logic data is determined. When the logic data is in a first logic level, where a first reading current of the corresponding resistive memory cell is greater than a first reference current, a set pulse and a reset pulse are provided to the resistive memory cell during a writing period. When the logic data is in a second logic level, where a second reading current of the resistive memory cell is smaller than a second reference current, the reset pulse is provided to the resistive memory cell during the writing period. Polarities of the reset pulse and the set pulse are opposite.
Abstract translation: 提供了一种电阻式存储装置及其写入方法。 在该方法中，接收逻辑数据，并且选择相应的电阻性存储单元。 确定逻辑数据的逻辑电平。 当逻辑数据处于第一逻辑电平（其中对应的电阻性存储单元的第一读取电流大于第一参考电流）时，在写入周期期间将设置脉冲和复位脉冲提供给电阻存储器单元。 当逻辑数据处于第二逻辑电平时，其中电阻存储单元的第二读取电流小于第二参考电流，在写入周期期间将复位脉冲提供给电阻存储单元。 复位脉冲和设定脉冲的极性相反。
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公开(公告)号：US20160055906A1
公开(公告)日：2016-02-25
申请号：US14463625
申请日：2014-08-19
Applicant: Winbond Electronics Corp.
Inventor： Chia-Hua Ho , Shao-Ching Liao , Ping-Kun Wang , Meng-Hung Lin
IPC: G11C13/00
Abstract: An operation method of a resistive random access memory (RRAM) cell is provided, wherein the RRAM cell includes a variable impedance element and a switch element connected in series. The operation method includes the following steps. When the switch element is turned-on, a writing signal is provided to the variable impedance element to set an impedance of the variable impedance element. In a first period, the writing signal is set to a first writing voltage level to transmit a first electrical energy to the variable impedance element. In a second period, a second electrical energy is transmitted to the variable impedance element by the writing signal. The second period is subsequent to the first period, the first electrical energy and the second electrical energy are greater than zero, and the second electrical energy is smaller than the first electrical energy.
Abstract translation: 提供了一种电阻随机存取存储器（RRAM）单元的操作方法，其中RRAM单元包括串联连接的可变阻抗元件和开关元件。 操作方法包括以下步骤。 当开关元件导通时，向可变阻抗元件提供写入信号以设置可变阻抗元件的阻抗。 在第一时段中，将写入信号设置为第一写入电压电平以向可变阻抗元件发送第一电能。 在第二时段中，通过写入信号将第二电能传输到可变阻抗元件。 第二时期是在第一时段之后，第一电能和第二电能大于零，第二电能小于第一电能。
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公开(公告)号：US11972799B2
公开(公告)日：2024-04-30
申请号：US17683356
申请日：2022-03-01
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Chia-Hung Lin , Jun-Yao Huang
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0007 , G11C2013/0045
Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether rate of increase of saturating read current is less than first threshold value; when rate of increase of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether rate of increase of saturating read current is less than first threshold value; finishing the method when rate of increase of saturating read current is less than first threshold value and saturating read current reaches target current value.
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