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公开(公告)号：US07379067B2
公开(公告)日：2008-05-27
申请号：US11305474
申请日：2005-12-15
CPC分类号： G06T1/20 , G06T1/60 , G06T5/002 , G06T15/005
摘要： A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
摘要翻译： 高速环形拓扑。 在一个实施例中，需要两种基本芯片类型：“绘图”芯片，LoopDraw和“接口”芯片，LoopInterface。 每个芯片都有一组引脚，支持相同的高速点对点输入和输出环互连接口：LoopLink。 LoopDraw芯片使用额外的引脚连接到形成高带宽本地存储器子系统的多个标准存储器。 LoopInterface芯片使用额外的引脚来支持高速主机主机接口，至少一个视频输出接口，以及可能与其他LoopInterface芯片的附加非本地互连。
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公开(公告)号：US07145570B2
公开(公告)日：2006-12-05
申请号：US10317599
申请日：2002-12-12
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06T15/04
摘要： A system and a method for improving magnified texture-mapped pixel performance in a single-pixel pipeline. A plurality of textured pixel addresses corresponding to a plurality of pixels may be generated. A FIFO or other memory unit may be used to linearly order the plurality of textured pixel addresses. Two consecutive textured pixel addresses out of the plurality of textured pixel addresses may be examined if they map to a common set of texels in texture space. The two consecutive textured pixel addresses may be merged together and propagated down the pipeline if they map to the common set of texels. However, only a first of the two consecutive textured pixel addresses may be propagated down the pipeline if the two consecutive textured pixel addresses do not map to a common set of texels. Texel data may be generated in response to receiving either the combined texel structure or the first of the two textured pixel addresses. The texel data may be filtered using one or more texture filters in order to generate texture values. The next two textured pixel addresses that may be examined by the merge unit include the subsequent two consecutive textured pixel addresses, or a second of the two consecutive textured pixel addresses and a subsequent consecutive textured pixel address.
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公开(公告)号：US06906720B2
公开(公告)日：2005-06-14
申请号：US10096065
申请日：2002-03-12
CPC分类号： G06T1/60 , G06T11/40 , G09G5/363 , G09G5/39 , G09G2360/12
摘要： A graphics system may include a frame buffer, a processing device coupled to output data, a multipurpose memory device that includes a plurality of storage locations and is coupled to store data output from the processing device, and a multipurpose memory controller coupled to the multipurpose memory device. The multipurpose memory controller may be configured to allocate a first plurality of the storage locations to a first image buffer configured to store image data, a second plurality of the storage locations to a first texture buffer configured to store texture data, and a third plurality of the storage locations to a first accumulation buffer configured to store accumulation buffer data. The multipurpose memory device may be configured to include a first image buffer, a first texture buffer, and a first accumulation buffer at the same time.
摘要翻译： 图形系统可以包括帧缓冲器，耦合到输出数据的处理设备，包括多个存储位置并被耦合以存储从处理设备输出的数据的多用途存储器设备，以及耦合到多用途存储器的多用途存储器控制器 设备。 多用途存储器控制器可以被配置为将第一多个存储位置分配给被配置为存储图像数据的第一图像缓冲器，第二多个存储位置分配给被配置为存储纹理数据的第一纹理缓冲器，以及第三多个 存储位置到被配置为存储累积缓冲器数据的第一累积缓冲器。 多用途存储器装置可以被配置为同时包括第一图像缓冲器，第一纹理缓冲器和第一累积缓冲器。
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24.发明授权公开(公告)号：US06819320B2
公开(公告)日：2004-11-16
申请号：US10090479
申请日：2002-03-04
申请人： Michael G. Lavelle , Elena M. Ing
发明人： Michael G. Lavelle , Elena M. Ing
IPC分类号： G06F1500
CPC分类号： G06T5/002 , G06T5/20 , G06T2200/12 , G06T2207/10016
摘要： A graphics system and method for storing pixel values into or reading pixel values from a sample buffer, wherein the sample buffer is configured to store a plurality of samples for each of a plurality of pixels. The graphics system comprises a sample buffer, a programmable register, and a graphics processor. The programmable register stores a value indicating a method for pixel to sample conversion, and is preferably software programmable (e.g., user programmable). The graphics processor accesses the memory to determine a method for pixel to sample conversion and stores the pixel values in the sample buffer according to the determined method. A first method for pixel to sample conversion may specify a pixel write to all of the pixel's supporting samples. A second method for pixel to sample conversion may specify a pixel write to a selected one of the pixel's supporting samples.
摘要翻译： 一种用于将像素值存储到样本缓冲器中或从其中读取像素值的图形系统和方法，其中所述采样缓冲器被配置为存储多个像素中的每一个的多个采样。 图形系统包括采样缓冲器，可编程寄存器和图形处理器。 可编程寄存器存储指示用于像素到样本转换的方法的值，并且优选地是软件可编程的（例如，用户可编程的）。 图形处理器访问存储器以确定用于像素进行采样转换的方法，并根据确定的方法将像素值存储在采样缓冲器中。 用于像素进行采样转换的第一种方法可以指定对所有像素的支持样本的像素写入。 用于像素到采样转换的第二种方法可以指定对所选像素的支持样本中的所选择的像素的像素写入。
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公开(公告)号：US06795081B2
公开(公告)日：2004-09-21
申请号：US09861479
申请日：2001-05-18
申请人： Michael G. Lavelle , Philip C. Leung , Yan Y. Tang
发明人： Michael G. Lavelle , Philip C. Leung , Yan Y. Tang
IPC分类号： G09G536
CPC分类号： G06T1/60
摘要： A system and method capable of super-sampling and performing super-sample convolution are disclosed. In one embodiment, the system may comprise a graphics processor, a frame buffer, a sample cache, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples. The frame buffer, which is coupled to the graphics processor, may be configured to store the samples in a sample buffer. The samples may be positioned according to a regular grid, a perturbed regular grid, or a stochastic grid. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the frame buffer, copy the selected samples to a sample cache, and filter a set of the selected samples into an output pixel. The sample-to-pixel calculation unit retains those samples in the sample cache that will be reused in a subsequent pixel calculation and replaces those samples no longer required with new samples for another filter calculation.
摘要翻译： 公开了能够超采样和执行超采样卷积的系统和方法。 在一个实施例中，系统可以包括图形处理器，帧缓冲器，采样高速缓存和采样到像素计算单元。 图形处理器可以被配置为生成多个采样。 耦合到图形处理器的帧缓冲器可以被配置为将样本存储在采样缓冲器中。 样本可以根据规则网格，扰动的规则网格或随机网格来定位。 样本到像素计算单元是可编程的，以从帧缓冲器中选择可变数量的存储样本，将所选样本复制到样本高速缓存，并将所选择的样本集合过滤到输出像素中。 样本到像素计算单元将样本缓存中保留的样本保留在随后的像素计算中重新使用，并将不再需要的样本替换为另一个滤波器计算的新采样。
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26.发明授权公开(公告)号：US06670959B2
公开(公告)日：2003-12-30
申请号：US09861481
申请日：2001-05-18
IPC分类号： G06F1318
CPC分类号： G09G5/001 , G06F3/1431 , G06F13/1605 , G09G3/003 , G09G5/006 , G09G5/346 , G09G5/393 , G09G5/395 , G09G2360/128 , G09G2360/18
摘要： A graphics system that may be shared between multiple display channels includes a frame buffer, an arbiter, and two pixel output buffers. The arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer is divided into a first and a second portion. The arbiter alternates display channel requests for data between the first and second portions of the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the output buffers. The arbiter selects which request to forward to the frame buffer based on a relative state of neediness of each of the requesting display channels.
摘要翻译： 可以在多个显示通道之间共享的图形系统包括帧缓冲器，仲裁器和两个像素输出缓冲器。 仲裁者在显示通道对帧缓冲器的显示信息请求之间进行仲裁，并将所选择的请求转发到帧缓冲器。 帧缓冲器被分成第一和第二部分。 仲裁器交替显示帧缓冲器的第一和第二部分之间的数据的信道请求。 帧缓冲器响应于接收转发的请求而输出显示信息，并且与该显示信息相对应的像素被存储在输出缓冲器中。 仲裁器根据每个请求显示通道的相关状态选择哪个请求转发到帧缓冲器。
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公开(公告)号：US06654021B2
公开(公告)日：2003-11-25
申请号：US09861461
申请日：2001-05-18
申请人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Nathaniel David Naegle , Steven Te-Chun Yu , Glenn Gracon
发明人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Nathaniel David Naegle , Steven Te-Chun Yu , Glenn Gracon
IPC分类号： G06F1318
CPC分类号： G09G5/12 , G06F3/1431 , G09G5/395 , G09G2360/123
摘要： A graphics system that may be shared between multiple display channels includes a frame buffer, two arbiters, a pixel buffer, and several display output queues. The first arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the pixel buffer. Each display channel has a corresponding display output queue that provides data to a display and generates a request for pixels from the pixel buffer. A pixel request arbiter receives the pixel requests generated by the display output queues, selects one of the pixel requests, and forwards the selected request to the pixel buffer. In response, the pixel buffer outputs pixels to the display output queue that generated the selected pixel request.
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公开(公告)号：US5579473A
公开(公告)日：1996-11-26
申请号：US276814
申请日：1994-07-18
IPC分类号： G06F12/00 , C04B28/08 , G06F12/08 , G06T11/00 , G09G5/00 , G09G5/39 , G09G5/393 , G09G5/397 , G09G5/399 , G06F15/00
CPC分类号： G09G5/393 , G06F12/0897 , G09G5/39 , G09G2360/121 , G09G2360/123
摘要： A frame buffer memory device controller that schedules and dispatches operations to frame buffer memory devices is disclosed. The frame buffer memory device controller schedules and dispatches cache control operations to reduce timing overheads caused by cache prefetch operations, and operations to write back dirty cache lines and clear cache lines in the frame buffer memory devices. The frame buffer memory device controller also schedules and dispatches control operations to reduce timing overheads caused by video refresh operations from the frame buffer memory devices video output ports.
摘要翻译： 公开了一种对帧缓冲存储器件进行调度和调度操作的帧缓冲存储器件控制器。 帧缓冲存储器设备控制器调度和调度高速缓存控制操作以减少由高速缓存预取操作引起的定时开销，以及写入脏高速缓存行并清除帧缓冲存储器设备中的高速缓存行的操作。 帧缓冲存储器件控制器还调度和调度控制操作以减少由帧缓冲存储器件视频输出端口的视频刷新操作引起的定时开销。
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公开(公告)号：US07808505B2
公开(公告)日：2010-10-05
申请号：US12127737
申请日：2008-05-27
CPC分类号： G06T1/20 , G06T1/60 , G06T5/002 , G06T15/005
摘要： A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
摘要翻译： 高速环形拓扑。 在一个实施例中，需要两种基本芯片类型：“绘图”芯片，LoopDraw和“接口”芯片，LoopInterface。 每个芯片都有一组引脚，支持相同的高速点对点输入和输出环互连接口：LoopLink。 LoopDraw芯片使用额外的引脚连接到形成高带宽本地存储器子系统的多个标准存储器。 LoopInterface芯片使用额外的引脚来支持高速主机主机接口，至少一个视频输出接口，以及可能与其他LoopInterface芯片的附加非本地互连。
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30.发明授权公开(公告)号：US07599439B2
公开(公告)日：2009-10-06
申请号：US11166458
申请日：2005-06-24
IPC分类号： H04N7/18
CPC分类号： G06F3/14 , G09G3/2092 , G09G5/006
摘要： A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N≠K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the transmitter is typically configured also to transmit over the link packing phase data indicative of the phase of the most recently transmitted fragment. Other aspects are transmitters and receivers for use in such a system and methods implemented by any such transmitter, receiver, or system.
摘要翻译： 包括接收机，TMDS链路（或其他串行链路）的系统和被配置为通过链路发送K位视频字（通常为编码的8位视频字）的发射机。 在典型的实施例中，发射机被配置为将N个比特视频字序列打包到一个K比特片段序列中，其中N
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