-
1.发明授权公开(公告)号：US06670959B2
公开(公告)日：2003-12-30
申请号：US09861481
申请日：2001-05-18
IPC分类号： G06F1318
CPC分类号： G09G5/001 , G06F3/1431 , G06F13/1605 , G09G3/003 , G09G5/006 , G09G5/346 , G09G5/393 , G09G5/395 , G09G2360/128 , G09G2360/18
摘要： A graphics system that may be shared between multiple display channels includes a frame buffer, an arbiter, and two pixel output buffers. The arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer is divided into a first and a second portion. The arbiter alternates display channel requests for data between the first and second portions of the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the output buffers. The arbiter selects which request to forward to the frame buffer based on a relative state of neediness of each of the requesting display channels.
摘要翻译： 可以在多个显示通道之间共享的图形系统包括帧缓冲器，仲裁器和两个像素输出缓冲器。 仲裁者在显示通道对帧缓冲器的显示信息请求之间进行仲裁，并将所选择的请求转发到帧缓冲器。 帧缓冲器被分成第一和第二部分。 仲裁器交替显示帧缓冲器的第一和第二部分之间的数据的信道请求。 帧缓冲器响应于接收转发的请求而输出显示信息，并且与该显示信息相对应的像素被存储在输出缓冲器中。 仲裁器根据每个请求显示通道的相关状态选择哪个请求转发到帧缓冲器。
-
公开(公告)号：US06654021B2
公开(公告)日：2003-11-25
申请号：US09861461
申请日：2001-05-18
申请人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Nathaniel David Naegle , Steven Te-Chun Yu , Glenn Gracon
发明人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Nathaniel David Naegle , Steven Te-Chun Yu , Glenn Gracon
IPC分类号： G06F1318
CPC分类号： G09G5/12 , G06F3/1431 , G09G5/395 , G09G2360/123
摘要： A graphics system that may be shared between multiple display channels includes a frame buffer, two arbiters, a pixel buffer, and several display output queues. The first arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the pixel buffer. Each display channel has a corresponding display output queue that provides data to a display and generates a request for pixels from the pixel buffer. A pixel request arbiter receives the pixel requests generated by the display output queues, selects one of the pixel requests, and forwards the selected request to the pixel buffer. In response, the pixel buffer outputs pixels to the display output queue that generated the selected pixel request.
-
3.发明授权Rasterization using two-dimensional tiles and alternating bins for improved rendering utilization 有权使用二维瓦片和交替箱体进行光栅化，以提高渲染利用率公开(公告)号：US06803916B2
公开(公告)日：2004-10-12
申请号：US09861475
申请日：2001-05-18
申请人： Nandini Ramani , David C. Kehlet , Ewa M. Kubalska , Michael G. Lavelle , Michael A. Wasserman , Kevin Tang , Yan Yan Tang
发明人： Nandini Ramani , David C. Kehlet , Ewa M. Kubalska , Michael G. Lavelle , Michael A. Wasserman , Kevin Tang , Yan Yan Tang
IPC分类号： G06T120
摘要： A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the system's rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.
摘要翻译： 公开了一种用于光栅化和渲染图形数据的系统和方法。 顶点可以被分组以形成诸如三角形的图元，其使用样本仓的二维阵列进行光栅化。 可以根据诸如存储体分配的不同标准从箱中选择单个样本，以提高系统的渲染管线的利用率。 由于阵列可以具有比渲染流水线中的评估单元数更多的存储单元，所以来自存储区的样本可以被存储到FIFO存储器中以允许去除无效或空的样本（被渲染的原始图像之外的样本）。 然后可以对样本进行滤波以形成可显示以在显示装置上形成图像的像素。
-
4.发明授权Graphics primitive size estimation and subdivision for use with a texture accumulation buffer 有权用于纹理累积缓冲区的图形原始尺寸估计和细分公开(公告)号：US06914610B2
公开(公告)日：2005-07-05
申请号：US09861192
申请日：2001-05-18
申请人： Michael G. Lavelle , Wayne A. Morse , Rangit S. Oberoi , David C. Kehlet , Michael A. Wasserman , Brian D. Emberling , Roger C. Swanson
发明人： Michael G. Lavelle , Wayne A. Morse , Rangit S. Oberoi , David C. Kehlet , Michael A. Wasserman , Brian D. Emberling , Roger C. Swanson
摘要： A graphics system configured to apply multiple layers of texture information to primitives. The graphics system receives parameters defining a primitive and performs a size test on the primitive. If the size test cannot guarantee that a fragment size of the primitive is less than or equal to a fragment capacity of a texture accumulation buffer, the primitive is divided into subprimitives, and the graphics system applies the multiple layers of texture to fragments which intersect the primitive. The graphics system switches from a current layer to the layer next when it has applied textures corresponding to the current layer to all the fragments intersecting the primitive. The graphics system stores color values associated with the primitive fragments in the texture accumulation buffer between the application of successive texture layers.
摘要翻译： 图形系统被配置为将多层纹理信息应用于原语。 图形系统接收定义原语的参数，并对原语进行大小测试。 如果大小测试不能保证原语的片段大小小于或等于纹理累加缓冲区的片段容量，则将原语划分为子标识符，并且图形系统将多层纹理应用于与 原始。 当图形系统将与当前层对应的纹理应用于与图元相交的所有片段时，图形系统将从当前图层切换到该图层。 图形系统在连续纹理层的应用之间存储与纹理累积缓冲器中的原始片段相关联的颜色值。
-
公开(公告)号：US06833834B2
公开(公告)日：2004-12-21
申请号：US10021096
申请日：2001-12-12
IPC分类号： G06F1300
CPC分类号： G09G3/006 , G06F3/1431 , G09G5/001 , G09G5/18 , G09G5/363 , G09G5/395 , G09G2360/123
摘要： A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.
摘要翻译： 图形系统包括帧缓冲器，写地址生成器和像素缓冲器。 从帧缓冲器接收到的像素突发可能不是显示顺序。 在一个实施例中，写地址生成器计算从帧缓冲器输出的像素突发中的每个像素的写入地址。 写入地址对应于每个相应像素的突发内的相对显示顺序。 突发中的每个像素被存储到像素缓冲器中的其写入地址。 这样，突发中的像素以像素缓冲器内的显示顺序存储。
-
6.发明授权Multi-texturing by walking an appropriately-sized supertile over a primitive 有权通过在原始图像上行走适当尺寸的超重物进行多纹理化公开(公告)号：US07023444B2
公开(公告)日：2006-04-04
申请号：US10393528
申请日：2003-03-20
申请人： Brian D. Emberling , Michael G. Lavelle , Assana M. Fard , Nandini Ramani , David C. Kehlet , Michael A. Wasserman , Ewa M. Kubalska , Mark E Pascual
发明人： Brian D. Emberling , Michael G. Lavelle , Assana M. Fard , Nandini Ramani , David C. Kehlet , Michael A. Wasserman , Ewa M. Kubalska , Mark E Pascual
IPC分类号： G06T11/40
CPC分类号： G06T15/04
摘要： A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.
摘要翻译： 渲染单元定位一个supertile，以便它与一个原语相交。 渲染单元重复地移动超重物料箱，在所述重复步行的每次迭代中将一层纹理施加到上层的仓上。 渲染单元在将当前纹理层应用于上层的每个候选块之后前进到下一个纹理层。 每个纹理层应用于存储区的结果可以存储在纹理累积缓冲器中。 supertile的大小对应于纹理累积缓冲区的大小。 将最后一层纹理应用于上层的仓后，超级可以提前到一个新的位置。 渲染单元用优先级遍历原始图像，使得由supertile访问的区域的联合覆盖原始图像。
-
7.发明授权公开(公告)号：US06795080B2
公开(公告)日：2004-09-21
申请号：US10060954
申请日：2002-01-30
申请人： Michael G. Lavelle , David C. Kehlet , Michael A. Wasserman , Nandini Ramani , Ranjit S. Oberoi
发明人： Michael G. Lavelle , David C. Kehlet , Michael A. Wasserman , Nandini Ramani , Ranjit S. Oberoi
IPC分类号： G06T1140
CPC分类号： G06T11/001
摘要： A graphics system configured to apply multiple layers of texture information to batches of primitives. The graphics system collects primitives into a batch that share a common set of texture layers to be applied. The batch is limited so that the total estimate size of the batch is less than or equal to a storage capacity of a texture accumulation buffer. The graphics system stores samples (or fragments) corresponding to the batch primitives in the texture accumulation buffer between the application of successive texture layers.
摘要翻译： 图形系统被配置为将多层纹理信息应用于批量的图元。 图形系统将基元收集到共享要应用的一组公共纹理图层的批次中。 批量被限制，使得批次的总估计大小小于或等于纹理累积缓冲器的存储容量。 图形系统将相应于批量原语的样本（或片段）存储在连续纹理层的应用之间的纹理累积缓冲器中。
-
公开(公告)号：US5862150A
公开(公告)日：1999-01-19
申请号：US963261
申请日：1997-10-28
IPC分类号： G06F3/153 , G06F11/277 , G09G5/00 , G09G5/18 , G09G5/395 , G09G5/397 , G09G5/399 , G06F15/20
CPC分类号： G09G5/395 , G06F11/277
摘要： A method and apparatus for performing signature analysis of video data being output by a RAMDAC so that starting and stopping the sampling of data is made precise so that the data sampled is a known set. The invention uses a timing generator and signature analysis hardware integrated with a RAMDAC to start and stop the sampling and signature calculation of video data on frame boundaries. A signature capture request bit is used to request that the next frame be sampled and a signature calculated. The hardware waits until the beginning of the next frame starts, and then samples data until the frame ends. The calculated signature is made available in a signature analysis result register for reading. The resulting signature is held in the signature analysis result register until cleared or another signature capture request is made.
摘要翻译： 一种用于执行由RAMDAC输出的视频数据的签名分析的方法和装置，使得开始和停止数据采样是精确的，使得采样的数据是已知的集合。 本发明使用与RAMDAC集成的定时发生器和签名分析硬件来启动和停止帧边界上的视频数据的采样和签名计算。 签名捕获请求位用于请求下一帧被采样并计算签名。 硬件等待直到下一帧开始，然后采样数据直到帧结束。 计算的签名在签名分析结果寄存器中可用于阅读。 结果签名保存在签名分析结果寄存器中，直到清除或另一个签名捕获请求。
-
公开(公告)号：US5696534A
公开(公告)日：1997-12-09
申请号：US408272
申请日：1995-03-21
CPC分类号： G09G5/395
摘要： A method and for multiplexing pixel data from a frame buffer to a RAMDAC to reduce the number of pins required. For many graphics operations optimal performance is achieved by storing an entire 32-bit pixel in a single RAM chip. When displaying video data from a frame buffer, pixels must be read out serially from the frame buffer at real-time speeds. A frame buffer memory with 16 pins for serial video output is used. An entire 32-bit pixel is stored in a single RAM chip. For a 32-bit pixel containing four byte (8-bit) quantities designated X, B, G and R, on the first clock cycle, the X and B bytes are made available on the 16 pins of the frame buffer. On the next clock cycle, the G and R bytes are made available. Thus, over two cycles the entire 32-bit pixel is output from the frame buffer to a RAMDAC which samples the X and B bytes on 16 input pins. The RAMDAC stores these X and B bytes in an internal register. On the next clock cycle it samples the G and R bytes. The DAC then reassembles the X, B, G and R bytes into a single 32-bit pixel for conversion into video. In this manner, 32-bit pixels are communicated across a 16-bit pixel data bus.
摘要翻译： 一种用于将来自帧缓冲器的像素数据复用到RAMDAC的方法，以减少所需的引脚数。 对于许多图形操作，通过将整个32位像素存储在单个RAM芯片中来实现最佳性能。 当从帧缓冲器显示视频数据时，像素必须以实时速度从帧缓冲器中串行读出。 使用具有16个引脚用于串行视频输出的帧缓冲存储器。 整个32位像素存储在单个RAM芯片中。 对于包含在第一个时钟周期指定为X，B，G和R的四个字节（8位）的32位像素，X和B字节在帧缓冲器的16个引脚上可用。 在下一个时钟周期中，G和R字节可用。 因此，在两个周期内，整个32位像素从帧缓冲器输出到RAMDAC，其对16个输入引脚上的X和B字节进行采样。 RAMDAC将这些X和B字节存储在内部寄存器中。 在下一个时钟周期，它对G和R字节进行采样。 然后，DAC将X，B，G和R字节重新组合成单个32位像素，以转换为视频。 以这种方式，32位像素在16位像素数据总线上传送。
-
10.发明授权Graphics data synchronization with multiple data paths in a graphics accelerator 有权图形数据同步与图形加速器中的多个数据路径公开(公告)号：US06864892B2
公开(公告)日：2005-03-08
申请号：US10093835
申请日：2002-03-08
CPC分类号： G09G5/36 , G06T15/005
摘要： A system and method for preserving the order of data items through a divergence-and-reconvergence of two or more paths in a hardware device. A host processor may write a first token to a first path in the hardware device. A convergence unit in the hardware device may receive and store the first token in a synchronization register. The host processor may poll the synchronization register to determine when the first token arrives in the synchronization register. In response to determining that the first token has arrived in the synchronization register, the host processor may safely write a sequence of one or more data items to a second path in the hardware device.
摘要翻译： 一种用于通过硬件设备中两个或多个路径的发散和再聚合来保持数据项的顺序的系统和方法。 主处理器可以将第一令牌写入硬件设备中的第一路径。 硬件设备中的会聚单元可以将第一令牌接收并存储在同步寄存器中。 主处理器可以轮询同步寄存器以确定第一个令牌何时到达同步寄存器。 响应于确定第一令牌已经到达同步寄存器，主处理器可以安全地将一个或多个数据项的序列写入硬件设备中的第二路径。
-
-
-
-
-
-
-
-
-
搜索结果
15 条记录 (耗时 0.026 秒)
