-
公开(公告)号：US08593468B2
公开(公告)日：2013-11-26
申请号：US12898249
申请日：2010-10-05
CPC分类号： G06T1/20 , G06T1/60 , G06T5/002 , G06T15/005
摘要： A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
摘要翻译： 高速环形拓扑。 在一个实施例中，需要两种基本芯片类型：“绘图”芯片，LoopDraw和“接口”芯片，LoopInterface。 每个芯片都有一组引脚，支持相同的高速点对点输入和输出环互连接口：LoopLink。 LoopDraw芯片使用额外的引脚连接到形成高带宽本地存储器子系统的多个标准存储器。 LoopInterface芯片使用额外的引脚来支持高速主机主机接口，至少一个视频输出接口，以及可能与其他LoopInterface芯片的附加非本地互连。
-
公开(公告)号：US20110221742A1
公开(公告)日：2011-09-15
申请号：US12898249
申请日：2010-10-05
IPC分类号： G06T15/00
CPC分类号： G06T1/20 , G06T1/60 , G06T5/002 , G06T15/005
摘要： A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
摘要翻译： 高速环形拓扑。 在一个实施例中，需要两种基本芯片类型：“绘图”芯片，LoopDraw和“接口”芯片，LoopInterface。 每个芯片都有一组引脚，支持相同的高速点对点输入和输出环互连接口：LoopLink。 LoopDraw芯片使用额外的引脚连接到形成高带宽本地存储器子系统的多个标准存储器。 LoopInterface芯片使用额外的引脚来支持高速主机主机接口，至少一个视频输出接口，以及可能与其他LoopInterface芯片的附加非本地互连。
-
公开(公告)号：US07379067B2
公开(公告)日：2008-05-27
申请号：US11305474
申请日：2005-12-15
CPC分类号： G06T1/20 , G06T1/60 , G06T5/002 , G06T15/005
摘要： A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
摘要翻译： 高速环形拓扑。 在一个实施例中，需要两种基本芯片类型：“绘图”芯片，LoopDraw和“接口”芯片，LoopInterface。 每个芯片都有一组引脚，支持相同的高速点对点输入和输出环互连接口：LoopLink。 LoopDraw芯片使用额外的引脚连接到形成高带宽本地存储器子系统的多个标准存储器。 LoopInterface芯片使用额外的引脚来支持高速主机主机接口，至少一个视频输出接口，以及可能与其他LoopInterface芯片的附加非本地互连。
-
公开(公告)号：US06943791B2
公开(公告)日：2005-09-13
申请号：US10094947
申请日：2002-03-11
CPC分类号： G06T15/005 , G06T2200/28
摘要： A system and method are disclosed for utilizing a Z slope test to select polygons that may be candidates for multiple storage methods. The method may calculate the absolute Z slope from vertex data and compare the calculated value with a specified threshold value. In some embodiments, for polygons that have an absolute Z slope less than the threshold value, parameter values may be rendered for only one sample position of multiple neighboring sample positions. The parameter values rendered for the one sample position may then be stored in multiple memory locations that correspond to the multiple neighboring sample positions. In some embodiments, storing parameter values in multiple memory locations may be achieved in a single write transaction. In some embodiments, utilization of the Z slope test method may be subject to user input and in other embodiments may be a dynamic decision controlled by the graphics system.
摘要翻译： 公开了一种利用Z斜率测试来选择可能是多种存储方法候选的多边形的系统和方法。 该方法可以从顶点数据计算绝对Z斜率，并将计算值与指定的阈值进行比较。 在一些实施例中，对于具有小于阈值的绝对Z斜率的多边形，可以仅为多个相邻采样位置的一个采样位置呈现参数值。 然后可以将针对一个采样位置渲染的参数值存储在对应于多个相邻采样位置的多个存储器位置中。 在一些实施例中，在多个存储器位置中存储参数值可以在单个写入事务中实现。 在一些实施例中，Z斜率测试方法的利用可能受用户输入的限制，在其他实施例中可以是由图形系统控制的动态决策。
-
公开(公告)号：US5579473A
公开(公告)日：1996-11-26
申请号：US276814
申请日：1994-07-18
IPC分类号： G06F12/00 , C04B28/08 , G06F12/08 , G06T11/00 , G09G5/00 , G09G5/39 , G09G5/393 , G09G5/397 , G09G5/399 , G06F15/00
CPC分类号： G09G5/393 , G06F12/0897 , G09G5/39 , G09G2360/121 , G09G2360/123
摘要： A frame buffer memory device controller that schedules and dispatches operations to frame buffer memory devices is disclosed. The frame buffer memory device controller schedules and dispatches cache control operations to reduce timing overheads caused by cache prefetch operations, and operations to write back dirty cache lines and clear cache lines in the frame buffer memory devices. The frame buffer memory device controller also schedules and dispatches control operations to reduce timing overheads caused by video refresh operations from the frame buffer memory devices video output ports.
摘要翻译： 公开了一种对帧缓冲存储器件进行调度和调度操作的帧缓冲存储器件控制器。 帧缓冲存储器设备控制器调度和调度高速缓存控制操作以减少由高速缓存预取操作引起的定时开销，以及写入脏高速缓存行并清除帧缓冲存储器设备中的高速缓存行的操作。 帧缓冲存储器件控制器还调度和调度控制操作以减少由帧缓冲存储器件视频输出端口的视频刷新操作引起的定时开销。
-
公开(公告)号：US07808505B2
公开(公告)日：2010-10-05
申请号：US12127737
申请日：2008-05-27
CPC分类号： G06T1/20 , G06T1/60 , G06T5/002 , G06T15/005
摘要： A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
摘要翻译： 高速环形拓扑。 在一个实施例中，需要两种基本芯片类型：“绘图”芯片，LoopDraw和“接口”芯片，LoopInterface。 每个芯片都有一组引脚，支持相同的高速点对点输入和输出环互连接口：LoopLink。 LoopDraw芯片使用额外的引脚连接到形成高带宽本地存储器子系统的多个标准存储器。 LoopInterface芯片使用额外的引脚来支持高速主机主机接口，至少一个视频输出接口，以及可能与其他LoopInterface芯片的附加非本地互连。
-
7.发明授权System and method for computing filtered shadow estimates using reduced bandwidth 有权使用减少的带宽计算滤波阴影估计的系统和方法公开(公告)号：US07106326B2
公开(公告)日：2006-09-12
申请号：US10378279
申请日：2003-03-03
CPC分类号： G06T15/60
摘要： A graphical processing system comprising a computational unit and a shadow processing unit coupled to the computational unit through a communication bus. The computational unit is configured to transfer coordinates C1 of a point P with respect to a first space to the shadow processing unit. In response to receiving the coordinates C1, the shadow processing unit is configured to: (a) transform the coordinate C1 to determine map coordinates s and t and a depth value Dp for the point P, (b) access a neighborhood of depth values from a memory using the map coordinates s and t, (c) compare the depth value DP to the depth values of the neighborhood, (d) filter binary results of the comparisons to determine a shadow fraction, and (e) transfer the shadow fraction to the computational unit through the communication bus.
摘要翻译： 一种图形处理系统，包括通过通信总线耦合到计算单元的计算单元和影子处理单元。 计算单元被配置为将点P相对于第一空间的坐标C 1 <1>传送到阴影处理单元。 阴影处理单元响应于接收坐标C 1＆lt; 1＆gt;，被配置为：（a）变换坐标C 1> 1以确定地图坐标s和t以及深度值 对于点P，（b）使用地图坐标s和t访问来自存储器的深度值的邻域，（c）比较深度值D （d）滤除比较的二进制结果以确定阴影分数，以及（e）通过通信总线将影子分数传送到计算单元。
-
8.发明授权Switching sample buffer context in response to sample requests for real-time sample filtering and video generation 有权响应样本请求进行实时样本过滤和视频生成，切换采样缓冲区上下文公开(公告)号：US06982719B2
公开(公告)日：2006-01-03
申请号：US10195827
申请日：2002-07-15
IPC分类号： G09G5/399
CPC分类号： G06T15/005 , G09G5/363
摘要： A graphics system configured with a scheduling network, a sample buffer, a rendering engine and a filtering engine. The rendering engine is configured to generate samples in response to received graphics data, and to forward the samples to the scheduling network for storage in the sample buffer. The filtering engine is configured to send a request for samples to the scheduling network. The scheduling network is configured to compare a video set designation of the request to a previous request designation, to update one or more state registers in one or more memory devices of the sample buffer in response to a determination that the video set designation of the request is different from the previous request designation, and to assert signals inducing a transfer of a collection of samples corresponding to the request from the one or more memory devices to the filtering engine.
摘要翻译： 配置有调度网络，采样缓冲器，呈现引擎和过滤引擎的图形系统。 渲染引擎被配置为响应于接收到的图形数据生成样本，并且将样本转发到调度网络以存储在采样缓冲器中。 过滤引擎被配置为向调度网络发送样本请求。 调度网络被配置为将请求的视频集指定与先前的请求指定进行比较，以响应于确定该请求的视频集指定，来更新采样缓冲器的一个或多个存储器设备中的一个或多个状态寄存器 与先前的请求指定不同，并且声明诱导将来自一个或多个存储器设备的对应于请求的样本集合传送到过滤引擎的信号。
-
公开(公告)号：US06459428B1
公开(公告)日：2002-10-01
申请号：US09970077
申请日：2001-10-03
申请人： Wayne Eric Burk , Yan Y. Tang , Michael G. Lavelle , Philip C. Leung , Michael F. Deering , Ranjit S. Oberoi
发明人： Wayne Eric Burk , Yan Y. Tang , Michael G. Lavelle , Philip C. Leung , Michael F. Deering , Ranjit S. Oberoi
IPC分类号： G06T1500
CPC分类号： G06T11/001 , G06T5/20 , G06T15/503
摘要： A graphics system configured to perform programmable filtering of samples to generate pixel values. The graphics system comprises a frame buffer, an accelerator unit and a video output processor. The accelerator unit receives graphics primitives, renders samples for the graphics primitives, and stores the rendered samples into a sample area of the frame buffer. The accelerator unit subsequently reads the samples from the sample area of the frame buffer, and filters the samples with a programmable filter having a programmable support region. The resulting pixel values are stored in a pixel area of the frame buffer. The video output processor reads the pixel values from the pixel area and converts the pixel values into a video signal which is provided to a video output port.
摘要翻译： 被配置为对样本执行可编程滤波以生成像素值的图形系统。 图形系统包括帧缓冲器，加速器单元和视频输出处理器。 加速器单元接收图形基元，呈现图形基元的样本，并将渲染的样本存储在帧缓冲器的采样区域中。 加速器单元随后从帧缓冲器的采样区域读取样本，并且用具有可编程支持区域的可编程滤波器对样本进行滤波。 所得到的像素值被存储在帧缓冲器的像素区域中。 视频输出处理器从像素区域读取像素值，并将像素值转换为提供给视频输出端口的视频信号。
-
10.发明授权Graphics system with multiported pixel buffers for accelerated pixel processing 有权具有多端口像素缓冲区的图形系统，用于加速像素处理公开(公告)号：US06195106B1
公开(公告)日：2001-02-27
申请号：US09479398
申请日：2000-01-06
IPC分类号： G09G536
CPC分类号： G09G5/39 , G06T15/005 , G09G5/399 , G09G2340/10 , G09G2360/121 , G09G2360/123 , G09G2360/126
摘要： A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.
摘要翻译： 公开了一种帧缓冲器动态随机存取存储器（FBRAM），其实现了Z缓冲图形基元的加速渲染。 FBRAM将读取 - 修改 - 写入事务（如Z缓冲区比较和RBG alpha混合）转换为只写操作。 FBRAM还实现了两级内部像素高速缓存和四路交错帧缓冲器。
-
-
-
-
-
-
-
-
-
搜索结果
125 条记录 (耗时 0.037 秒)
