公开(公告)号：US10673745B2

公开(公告)日：2020-06-02

申请号：US15886583

申请日：2018-02-01

Applicant: Xilinx, Inc.

Inventor： Ian A. Swarbrick ,  Ygal Arbel ,  Millind Mittal ,  Sagheer Ahmad

IPC: H04L12/725 ,  H04L12/851 ,  G06F15/78 ,  H04L12/931 ,  H04L29/08 ,  H04W4/50 ,  H04L12/933 ,  H04L12/701 ,  H04L12/70 ,  H04L12/863 ,  H04L12/721

Abstract: An example method of generating a configuration for a network on chip (NoC) in a programmable device includes: receiving traffic flow requirements for a plurality of traffic flows; assigning routes through the NoC for each traffic flow based on the traffic flow requirements; determining arbitration settings for the traffic flows along the assigned routes; generating programming data for the NoC; and loading the programming data to the programmable device to configure the NoC.

公开(公告)号：US20190266125A1

公开(公告)日：2019-08-29

申请号：US15904211

申请日：2018-02-23

Applicant: Xilinx, Inc.

Inventor： Ian A. Swarbrick

IPC: G06F15/78 ,  H04L12/24 ,  H04L12/933 ,  H04L29/06

Abstract: Embodiments herein describe a SoC that includes a programmable NoC that can be reconfigured to support different interface communication protocols. In one embodiment, the NoC includes ingress and egress logic blocks which permit hardware elements in the SoC (e.g., processors, memory, programmable logic blocks, etc.) to transmit and receive data using the NoC. The ingress and egress logic blocks may first be configured to support a particular communication protocol for interfacing with the hardware elements. However, at a later time, the user may wish to reconfigure the ingress and egress logic blocks to support a different communication protocol. In response, the SoC can reconfigure the NoC such that the ingress and egress logic blocks support the new communication protocol used by the hardware elements. In this manner, the programmable NoC can support multiple communication protocols used to interface with other hardware elements in the SoC.

公开(公告)号：US20190238453A1

公开(公告)日：2019-08-01

申请号：US15886583

申请日：2018-02-01

Applicant: Xilinx, Inc.

Inventor： Ian A. Swarbrick ,  Ygal Arbel ,  Millind Mittal ,  Sagheer Ahmad

IPC: H04L12/725 ,  H04L12/851 ,  H04L12/931 ,  G06F15/78

Abstract: An example method of generating a configuration for a network on chip (NoC) in a programmable device includes: receiving traffic flow requirements for a plurality of traffic flows; assigning routes through the NoC for each traffic flow based on the traffic flow requirements; determining arbitration settings for the traffic flows along the assigned routes; generating programming data for the NoC; and loading the programming data to the programmable device to configure the NoC.

公开(公告)号：US20190196901A1

公开(公告)日：2019-06-27

申请号：US15851449

申请日：2017-12-21

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Ian A. Swarbrick ,  Sagheer Ahmad

IPC: G06F11/10 ,  G11C29/52 ,  G06F13/16 ,  G06F15/78

CPC classification number: G06F15/7825 ,  G06F11/10 ,  G06F11/1068 ,  G06F13/1668 ,  G11C29/52

Abstract: An example integrated circuit (IC) includes a network-on-chip (NoC), a master device coupled to the NoC, a memory controller coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.