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公开(公告)号：US08275942B2
公开(公告)日：2012-09-25
申请号：US11316560
申请日：2005-12-22
CPC分类号： G06F12/0842
摘要： According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority hardware threads for processing by a multi-threaded processor in communication with the cache; assigning high priority hardware threads to the selected first subset; monitoring a cache usage of a high priority hardware thread assigned to the selected first subset of plurality of cache ways; and reassigning the assigned high priority hardware thread to any cache way of the plurality of cache ways if the cache usage of the high priority hardware thread exceeds a predetermined inactive cache usage threshold value based on the monitoring.
摘要翻译： 根据本发明的一个实施例，公开了一种用于选择高速缓存中的多个高速缓存路径的第一子集的方法，用于存储被识别为高优先级硬件线程的硬件线程，以用于与高速缓存通信的多线程处理器进行处理; 将高优先级的硬件线程分配给所选择的第一子集; 监视分配给所选择的多个高速缓存路线的第一子集的高优先级硬件线程的高速缓存使用; 以及如果所述高优先级硬件线程的高速缓存使用基于所述监视超过预定的非活动高速缓存使用阈值，则将所分配的高优先级硬件线程重新分配给所述多个高速缓存路径中的任何高速缓存方式。
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公开(公告)号：US10185566B2
公开(公告)日：2019-01-22
申请号：US13994142
申请日：2012-04-27
申请人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
发明人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
摘要： In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.
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23.发明授权公开(公告)号：US07711901B2
公开(公告)日：2010-05-04
申请号：US10779204
申请日：2004-02-13
CPC分类号： G06F12/128
摘要： A cache line replacement protocol for selecting a cache line for replacement based at least in part on the inter-cache traffic generated as a result of the cache line being replaced.
摘要翻译： 用于至少部分地基于作为高速缓存行被替换的结果生成的高速缓存间流量来选择用于替换的高速缓存行的高速缓存行替换协议。
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公开(公告)号：US20070186045A1
公开(公告)日：2007-08-09
申请号：US10897474
申请日：2004-07-23
IPC分类号： G06F12/00
CPC分类号： G06F12/128 , G06F12/0811 , G06F12/0897
摘要： A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the potential impact to other cache levels within the cache hierarchy.
摘要翻译： 一种用于智能驱逐包含缓存架构内的高速缓存行的技术。 更具体地，本发明的实施例涉及一种基于对高速缓存层级内的其他高速缓存级别的潜在影响来驱逐包容性高速缓存层级内的高速缓存行的技术。
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公开(公告)号：US07168074B1
公开(公告)日：2007-01-23
申请号：US09675286
申请日：2000-09-29
CPC分类号： G06Q30/02
摘要： A scaled-down representation of input to a compute-intensive application is created. A computing requirement based on the scaled-down representation is calculated. A turn-around time and an actual cost to a customer to run the compute-intensive application with the input, on one or more processors, based on the calculated computing requirement, is calculated and then sent to the customer.
摘要翻译： 创建对计算密集型应用程序的输入的缩小表示。 计算基于缩小表示的计算要求。 计算客户在一个或多个处理器上基于所计算的计算需求来输入计算密集型应用程序的周转时间和实际成本，然后将其发送给客户。
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26.发明授权Method, apparatus, and a system for dynamically configuring a prefetcher based on a thread specific latency metric 有权方法，装置和用于基于线程特定的等待时间度量动态配置预取器的系统公开(公告)号：US08079031B2
公开(公告)日：2011-12-13
申请号：US11256536
申请日：2005-10-21
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/383 , G06F12/0862 , G06F2212/502
摘要： A discussion of a dynamic configuration for a prefetcher is proposed. For example, a thread specific latency metric is calculated and provides dynamic feedback to the software on a per thread basis via the configuration and status registers. Likewise, the software can optionally use the information from the registers to dynamically configure the prefetching behavior and allows the software to be able to both query the performance and configure the prefetcher.
摘要翻译： 提出了对预取器的动态配置的讨论。 例如，计算线程特定的延迟度量，并通过配置和状态寄存器在每个线程的基础上向软件提供动态反馈。 同样，软件可以选择使用来自寄存器的信息来动态地配置预取行为，并允许软件能够查询性能并配置预取器。
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公开(公告)号：US07647476B2
公开(公告)日：2010-01-12
申请号：US11374708
申请日：2006-03-14
CPC分类号： G06F15/7832
摘要： In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via the digital interface circuitry. The analog interface may be used to communicate traffic between a package including the cores and an interconnect such as a shared bus coupled thereto. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有多个处理器核以执行指令的处理器，其中每个核包括专用数字接口电路。 处理器还包括经由数字接口电路耦合到核的模拟接口。 模拟接口可用于在包括核心的包和诸如耦合到其之间的共享总线的互连之间传送业务。 描述和要求保护其他实施例。
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公开(公告)号：US20070220233A1
公开(公告)日：2007-09-20
申请号：US11374708
申请日：2006-03-14
IPC分类号： G06F15/00
CPC分类号： G06F15/7832
摘要： In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via the digital interface circuitry. The analog interface may be used to communicate traffic between a package including the cores and an interconnect such as a shared bus coupled thereto. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有多个处理器核以执行指令的处理器，其中每个核包括专用数字接口电路。 处理器还包括经由数字接口电路耦合到核的模拟接口。 模拟接口可用于在包括核心的包和诸如耦合到其之间的共享总线的互连之间传送业务。 描述和要求保护其他实施例。
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