公开(公告)号：US08431291B2

公开(公告)日：2013-04-30

申请号：US13281198

申请日：2011-10-25

Applicant: George Liu ,  Kuei Shun Chen ,  Chih-Yang Yeh ,  Te-Chih Huang ,  Wen-Hao Liu ,  Ying-Chou Cheng ,  Boren Luo ,  Tsong-Hua Ou ,  Yu-Po Tang ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Shu-Chen Lu ,  Yu Lun Liu ,  Yao-Ching Ku ,  Tsai-Sheng Gau

Inventor： George Liu ,  Kuei Shun Chen ,  Chih-Yang Yeh ,  Te-Chih Huang ,  Wen-Hao Liu ,  Ying-Chou Cheng ,  Boren Luo ,  Tsong-Hua Ou ,  Yu-Po Tang ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Shu-Chen Lu ,  Yu Lun Liu ,  Yao-Ching Ku ,  Tsai-Sheng Gau

IPC: G03F1/00 ,  G03F1/36

CPC classification number: G06F17/5068 ,  G03F1/00 ,  G03F1/68

Abstract: An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.

Abstract translation: 还提供强度选择性曝光光掩模，还描述为渐变光掩模。 光掩模包括包括第一子分解特征阵列的第一区域。 第一个区域阻止了第一个入射辐射的百分比。 光掩模还包括包括第二子分辨率特征阵列的第二区域。 第二个区域阻止了第二个百分比的入射辐射不同于第一个百分比。

公开(公告)号：US08332797B2

公开(公告)日：2012-12-11

申请号：US12959150

申请日：2010-12-02

Applicant: Ying-Chou Cheng ,  Tsong-Hua Ou ,  Wen-Hao Liu ,  Ru-Gun Liu ,  Wen-Chun Huang

Inventor： Ying-Chou Cheng ,  Tsong-Hua Ou ,  Wen-Hao Liu ,  Ru-Gun Liu ,  Wen-Chun Huang

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  G06F2217/80 ,  Y02P90/265

Abstract: The present disclosure relates to parameterized dummy cell insertion for process enhancement and methods for fabricating the same. In accordance with one or more embodiments, methods include providing an integrated circuit (IC) design layout with defined pixel-units, simulating thermal effect to the IC design layout including each pixel-unit, generating a thermal effect map of the IC design layout including each pixel-unit, determining a target absorption value for the IC design layout, and performing thermal dummy cell insertion to each pixel-unit of the IC design layout based on the determined target absorption value.

Abstract translation: 本公开涉及用于过程增强的参数化虚拟单元插入及其制造方法。 根据一个或多个实施例，方法包括提供具有定义的像素单元的集成电路（IC）设计布局，模拟包括每个像素单元的IC设计布局的热效应，生成IC设计布局的热效应图，包括 每个像素单元，确定IC设计布局的目标吸收值，并且基于所确定的目标吸收值，向IC设计布局的每个像素单元执行热虚拟单元插入。

公开(公告)号：US20110289466A1

公开(公告)日：2011-11-24

申请号：US13195907

申请日：2011-08-02

Applicant: Yung-Chin Hou ,  Ying-Chou Cheng ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Yi-Kan Cheng ,  Chung-Kai Lin ,  Hsiao-Shu Chao ,  Ping-Heng Yeh ,  Min-Hong Wu ,  Yao-Ching Ku ,  Tsong-Hua Ou

Inventor： Yung-Chin Hou ,  Ying-Chou Cheng ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Yi-Kan Cheng ,  Chung-Kai Lin ,  Hsiao-Shu Chao ,  Ping-Heng Yeh ,  Min-Hong Wu ,  Yao-Ching Ku ,  Tsong-Hua Ou

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5081

Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.

Abstract translation: 公开了一种用于集成电路设计和后期布局分析的系统和方法。 集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。

公开(公告)号：US08037575B2

公开(公告)日：2011-10-18

申请号：US12211624

申请日：2008-09-16

Applicant: Ying-Chou Cheng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsong-Hua Ou ,  Min-Hong Wu ,  Yih-Yuh Doong ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Yao-Ching Ku ,  Cliff Hou

Inventor： Ying-Chou Cheng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsong-Hua Ou ,  Min-Hong Wu ,  Yih-Yuh Doong ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Yao-Ching Ku ,  Cliff Hou

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/12 ,  Y02P90/265 ,  Y10T16/2771

Abstract: An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.

Abstract translation: 集成电路（IC）设计方法包括基于IC器件的IC设计布局和IC制造数据提供IC布局轮廓; 生成有效的矩形布局来表示IC布局轮廓; 并使用有效的矩形布局模拟IC器件。

公开(公告)号：US20110124193A1

公开(公告)日：2011-05-26

申请号：US12625749

申请日：2009-11-25

Applicant: Ying-Chou Cheng ,  Ru-Gun Liu ,  Josh J.H. Feng ,  Tsong-Hua Ou ,  Luke Lo ,  Chih-Ming Lai ,  Wen-Chun Huang

Inventor： Ying-Chou Cheng ,  Ru-Gun Liu ,  Josh J.H. Feng ,  Tsong-Hua Ou ,  Luke Lo ,  Chih-Ming Lai ,  Wen-Chun Huang

IPC: H01L21/033 ,  G06F17/50

CPC classification number: G06F17/5068

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout.

Abstract translation: 本公开提供了集成电路（IC）设计方法的一个实施例。 该方法包括提供电路的IC设计布局; 根据电路的电气参数和IC设计布局的光学参数，对IC设计布局进行电气图案化（ePatterning）修改; 然后根据IC设计布局制造掩模。