公开(公告)号：US07812650B2

公开(公告)日：2010-10-12

申请号：US12157235

申请日：2008-06-09

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC分类号： H03L7/06

CPC分类号： H03L7/0893 ,  H03L7/099 ,  H03L7/107 ,  H03L2207/06

摘要： Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.

摘要翻译： 偏置电压发生器电路和时钟同步电路包括被配置为响应于带宽控制信号来控制电流的偏置单元，被配置为响应于由偏置单元控制的电流差异放大输入信号的放大单元和配置的输出单元 以接收放大单元的输出信号以输出偏置电压。

公开(公告)号：US07791391B2

公开(公告)日：2010-09-07

申请号：US12215829

申请日：2008-06-30

申请人： Dae-Kun Yoon ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Dae-Kun Yoon ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H03K5/13

CPC分类号： H03L7/0814 ,  H03K2005/00286 ,  H03L7/087

摘要： A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out, N-bit code values are stored according to a plurality of detected phase differences. A controller shares the N-bit code counter, controls the generation of the N-bit code values according to the plurality of detected phase differences, and controls the storing of the N-bit code values in an allocated space of the storage by use of a multiplexer configured to provide the plurality of detected phase differences to the N-bit code counter, and a demultiplexer configured to store the N-bit code values in the allocated space of the storage.

摘要翻译： 正交相位校正电路包括N比特码计数器，被配置为当执行正交相位校正时根据检测到的相位差产生N比特码值，根据多个检测相位存储N比特码值 差异 A控制器共享N位代码计数器，根据多个检测到的相位差控制N位代码值的产生，并且通过使用N位代码值来存储N位代码值到存储器的分配空间中 多路复用器，被配置为向N位代码计数器提供多个检测到的相位差，以及解复用器，被配置为将N位代码值存储在存储器的分配空间中。

公开(公告)号：US20090160560A1

公开(公告)日：2009-06-25

申请号：US12079443

申请日：2008-03-26

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03L7/00

CPC分类号： H03L7/0893 ,  H03L7/0896 ,  H03L7/0898

摘要： Phase locked loop and method for controlling the same includes a phase/frequency detector configured to detect a phase difference between an input clock and a feedback clock to generate an up signal or a down signal depending on the detected phase difference, a charge pump configured to variably control a bandwidth according to a bandwidth control signal input thereinto, the charge pump operating in response to the up signal or the down signal and a voltage controlled oscillator configured to change a frequency according to an output of the charge pump.

摘要翻译： 锁相环及其控制方法包括相位/频率检测器，被配置为检测输入时钟和反馈时钟之间的相位差，以根据检测到的相位差产生上升信号或下降信号，电荷泵被配置为 根据其中输入的带宽控制信号可变地控制带宽，所述电荷泵响应于上升信号或下降信号而工作;以及压控振荡器，被配置为根据电荷泵的输出来改变频率。

公开(公告)号：US20090160510A1

公开(公告)日：2009-06-25

申请号：US12157235

申请日：2008-06-09

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC分类号： H03L7/06 ,  H03K3/01

CPC分类号： H03L7/0893 ,  H03L7/099 ,  H03L7/107 ,  H03L2207/06

摘要： Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.

摘要翻译： 偏置电压发生器电路和时钟同步电路包括被配置为响应于带宽控制信号来控制电流的偏置单元，被配置为响应于由偏置单元控制的电流差异放大输入信号的放大单元和配置的输出单元 以接收放大单元的输出信号以输出偏置电压。

公开(公告)号：US20090115467A1

公开(公告)日：2009-05-07

申请号：US12005515

申请日：2007-12-27

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03B19/00 ,  G06F1/06

CPC分类号： G06F1/06

摘要： A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.

摘要翻译： 半导体存储器件可以基于多相时钟信号来优化布局面积和电流消耗，该多相时钟信号是通过使用没有延迟锁定环路和锁相环路的复位信号对源时钟信号进行分频而产生的，以便具有 低频和不同的激活时序具有恒定的相位差。

公开(公告)号：US20090115459A1

公开(公告)日：2009-05-07

申请号：US12005564

申请日：2007-12-27

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03K3/017 ,  H03K5/125

CPC分类号： H03K5/1565

摘要： A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to an operating frequency of the semiconductor device, and a duty ratio detecting unit for detecting a duty ratio of external clock signals in response to the enable signal.

摘要翻译： 一种半导体器件，包括：脉冲信号产生单元，用于产生彼此具有不同脉冲宽度的多个脉冲信号;信号复用单元，用于响应于一个或多个脉冲信号输出多个脉冲信号中的一个作为使能信号 半导体器件的工作频率以及响应于使能信号检测外部时钟信号的占空比的占空比检测单元。

公开(公告)号：US08283962B2

公开(公告)日：2012-10-09

申请号：US12005515

申请日：2007-12-27

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03K3/00

CPC分类号： G06F1/06

摘要： A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.

摘要翻译： 半导体存储器件可以基于多相时钟信号来优化布局面积和电流消耗，该多相时钟信号是通过使用没有延迟锁定环路和锁相环路的复位信号对源时钟信号进行分频而产生的，以便具有 低频和不同的激活时序具有恒定的相位差。

公开(公告)号：US08130890B2

公开(公告)日：2012-03-06

申请号：US12005492

申请日：2007-12-27

申请人： Kyung-Hoon Kim ,  Yong-Ki Kim ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Yong-Ki Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H04L7/02 ,  H04L7/04

CPC分类号： G11C29/02 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028

摘要： A data clock frequency divider circuit includes a training decoder and a frequency divider. The training decoder outputs a clock alignment training signal, which is indicative of the start of a clock alignment training, in response to a command and an address of a mode register set. The frequency divider, which is reset in response to an output of the training decoder, receives an internal data clock to divide a frequency of the internal data clock in half. The data clock frequency divider circuit secures a sufficient operating margin so that a data clock and a system clock are aligned within a pre-set clock training operation time by resetting the data clock to correspond to a timing in which the clock training operation starts, thereby providing a clock training for a high-speed system.

摘要翻译： 数据时钟分频器电路包括训练解码器和分频器。 响应于模式寄存器组的命令和地址，训练解码器输出表示时钟对准训练的开始的时钟对准训练信号。 响应于训练解码器的输出复位的分频器接收内部数据时钟以将内部数据时钟的频率分成两半。 数据时钟分频器电路确保足够的操作余量，使得数据时钟和系统时钟在预设的时钟训练操作时间内对齐，通过复位数据时钟以对应于时钟训练操作开始的定时，由此 为高速系统提供时钟训练。

公开(公告)号：US08130034B2

公开(公告)日：2012-03-06

申请号：US12833154

申请日：2010-07-09

申请人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

发明人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

IPC分类号： H03F3/45

CPC分类号： H03F3/45192

摘要： A rail-to-rail amplifier includes an NMOS type amplification unit configured to perform an amplification operation on differential input signals in a domain in which DC levels of the differential input signals are higher than a first threshold value, a PMOS type folded-cascode amplification unit configured to perform an amplification operation on the differential input signals in a domain in which the DC levels of the differential input signals are lower than a second threshold value which is higher than the first threshold value, the PMOS type folded-cascode amplification unit being cascade-coupled to the NMOS type amplification unit, and an adaptive biasing unit configured to interrupt a current path of the PMOS type folded-cascode amplification unit in a domain in which the DC levels of the differential input signals are higher than the second threshold value in response to the differential input signals.

摘要翻译： 轨到轨放大器包括：NMOS型放大单元，被配置为对差分输入信号的DC电平高于第一阈值的区域中的差分输入信号进行放大操作，PMOS型折叠共源共栅放大 被配置为对差分输入信号的DC电平低于高于第一阈值的第二阈值的区域中的差分输入信号进行放大操作的单元，PMOS型折叠共源共栅放大单元是 级联耦合到NMOS型放大单元，以及自适应偏置单元，被配置为在差分输入信号的DC电平高于第二阈值的区域中断PMOS型折叠共源共栅放大单元的电流路径 响应于差分输入信号。

公开(公告)号：US07952438B2

公开(公告)日：2011-05-31

申请号：US12217049

申请日：2008-06-30

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03B27/01

CPC分类号： H03L7/0812 ,  H03L7/18 ,  H03L7/24

摘要： An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

摘要翻译： 注入锁定时钟发生器可以改变注入锁定振荡器的自由运行频率，以扩大注入到其自身的振荡信号的工作频率范围，从而相对于工作频率范围的所有频率执行注入锁定。 时钟发生器包括：主振荡器，其被配置为产生与控制电压对应的频率的振荡信号;以及注入锁定振荡器，其被配置为通过划分所述振荡信号产生与所述振荡信号同步的除法信号，其中所述注入的自由运行频率 锁定振荡器根据振荡信号的频率设定。