公开(公告)号：US20090252457A1

公开(公告)日：2009-10-08

申请号：US12199517

申请日：2008-08-27

Applicant: Duk-Jun KIM ,  Jung-Ho Song ,  Jong-Moo Lee ,  Junghyung Pyo ,  Gyung-Ock Kim

Inventor： Duk-Jun KIM ,  Jung-Ho Song ,  Jong-Moo Lee ,  Junghyung Pyo ,  Gyung-Ock Kim

IPC: G02B6/26

CPC classification number: G02B6/12011 ,  G02B2006/12119

Abstract: Provided are a waveguide structure and an arrayed waveguide grating structure. The arrayed waveguide grating structure includes an input star coupler, an output star coupler, and a plurality of arrayed waveguides optically connecting the input star coupler and the output star coupler. Each of the arrayed waveguides includes at least one section having a high confinement factor and at least two sections having a relatively low confinement factor. The sections of the arrayed waveguides having a high confinement factor have the same structure.

Abstract translation: 提供了一种波导结构和阵列波导光栅结构。 阵列波导光栅结构包括输入星形耦合器，输出星形耦合器以及光学地连接输入星形耦合器和输出星形耦合器的多个阵列波导。 每个阵列波导包括具有高约束因子的至少一个部分和具有相对较低约束因子的至少两个部分。 具有高约束因子的阵列波导的部分具有相同的结构。

公开(公告)号：US08243530B2

公开(公告)日：2012-08-14

申请号：US12713219

申请日：2010-02-26

Applicant: Sang-Gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

Inventor： Sang-Gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

IPC: G11C5/14 ,  G11C7/00

CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C16/24 ,  G11C2207/005

Abstract: A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced.

Abstract translation: 非易失性存储器件包括反馈电路和预充电开关晶体管。 反馈电路在预充电操作期间基于位线的电压电平产生反馈信号。 响应于反馈信号，预充电开关晶体管控制用于预充电位线的预充电电流。 可以增加预充电操作的速度和/或可以减少对多个位线进行预充电的偏置信号的失配。

公开(公告)号：US20100034019A1

公开(公告)日：2010-02-11

申请号：US12533720

申请日：2009-07-31

Applicant: Sang-Gu Kang ,  Hee-won Lee ,  Ju Seok Lee ,  Jung-Ho Song

Inventor： Sang-Gu Kang ,  Hee-won Lee ,  Ju Seok Lee ,  Jung-Ho Song

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/24 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A nonvolatile memory system is operated by performing a program loop on each of a plurality of memory cells, each program loop comprising at least one program-verify operation and selectively pre-charging bit lines associated with each of the plurality of memory cells during the at least one program-verify operation.

Abstract translation: 通过在多个存储器单元中的每一个上执行程序循环来操作非易失性存储器系统，每个程序循环包括至少一个程序验证操作，并且在at期间选择性地预充电与多个存储器单元中的每一个相关联的位线 至少一个程序验证操作。

公开(公告)号：US20100002507A1

公开(公告)日：2010-01-07

申请号：US12472639

申请日：2009-05-27

Applicant: Sang-gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

Inventor： Sang-gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

IPC: G11C16/04 ,  G11C16/06 ,  G11C7/10

CPC classification number: G11C7/02 ,  G11C7/1048 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be programmed in a selected memory cell of the plurality of memory cells. The data input/output circuit maintains data to be programmed within the data input/output circuit during a program verify operation, and decreases noise in the common source line by selectively precharging the bit line based on the data to be programmed.

Abstract translation: 闪存器件控制公共源极线电压并执行程序验证方法。 多个存储单元连接在位线和公共源极线之间。 数据输入/输出电路连接到位线，并且被配置为存储要编程在多个存储器单元的所选存储单元中的数据。 数据输入/输出电路在编程验证操作期间保持在数据输入/输出电路内编程的数据，并且通过基于要编程的数据选择性地预充电位线来降低公共源极线中的噪声。