公开(公告)号：US20100220535A1

公开(公告)日：2010-09-02

申请号：US12713219

申请日：2010-02-26

申请人： Sang-Gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

发明人： Sang-Gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C5/147 ,  G11C16/24 ,  G11C2207/005

摘要： A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced.

摘要翻译： 非易失性存储器件包括反馈电路和预充电开关晶体管。 反馈电路在预充电操作期间基于位线的电压电平产生反馈信号。 响应于反馈信号，预充电开关晶体管控制用于预充电位线的预充电电流。 可以增加预充电操作的速度和/或可以减少对多个位线进行预充电的偏置信号的失配。

公开(公告)号：US08243530B2

公开(公告)日：2012-08-14

申请号：US12713219

申请日：2010-02-26

申请人： Sang-Gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

发明人： Sang-Gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C5/147 ,  G11C16/24 ,  G11C2207/005

摘要： A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced.

摘要翻译： 非易失性存储器件包括反馈电路和预充电开关晶体管。 反馈电路在预充电操作期间基于位线的电压电平产生反馈信号。 响应于反馈信号，预充电开关晶体管控制用于预充电位线的预充电电流。 可以增加预充电操作的速度和/或可以减少对多个位线进行预充电的偏置信号的失配。

公开(公告)号：US20100034019A1

公开(公告)日：2010-02-11

申请号：US12533720

申请日：2009-07-31

申请人： Sang-Gu Kang ,  Hee-won Lee ,  Ju Seok Lee ,  Jung-Ho Song

发明人： Sang-Gu Kang ,  Hee-won Lee ,  Ju Seok Lee ,  Jung-Ho Song

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/24 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： A nonvolatile memory system is operated by performing a program loop on each of a plurality of memory cells, each program loop comprising at least one program-verify operation and selectively pre-charging bit lines associated with each of the plurality of memory cells during the at least one program-verify operation.

摘要翻译： 通过在多个存储器单元中的每一个上执行程序循环来操作非易失性存储器系统，每个程序循环包括至少一个程序验证操作，并且在at期间选择性地预充电与多个存储器单元中的每一个相关联的位线 至少一个程序验证操作。

公开(公告)号：US08068361B2

公开(公告)日：2011-11-29

申请号：US12533720

申请日：2009-07-31

申请人： Sang-Gu Kang ,  Hee-won Lee ,  Ju Seok Lee ,  Jung-Ho Song

发明人： Sang-Gu Kang ,  Hee-won Lee ,  Ju Seok Lee ,  Jung-Ho Song

IPC分类号： G11C16/04

CPC分类号： G11C16/24 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： A nonvolatile memory system is operated by performing a program loop on each of a plurality of memory cells, each program loop comprising at least one program-verify operation and selectively pre-charging bit lines associated with each of the plurality of memory cells during the at least one program-verify operation.

摘要翻译： 通过在多个存储器单元中的每一个上执行程序循环来操作非易失性存储器系统，每个程序循环包括至少一个程序验证操作，并且在at期间选择性地预充电与多个存储器单元中的每一个相关联的位线 至少一个程序验证操作。

公开(公告)号：US07746719B2

公开(公告)日：2010-06-29

申请号：US12177323

申请日：2008-07-22

申请人： Sang-Gu Kang

发明人： Sang-Gu Kang

IPC分类号： G11C17/18

CPC分类号： G11C7/20 ,  G11C5/147

摘要： Disclosed is a multi-chip package having a plurality of memory chips. Each memory chip includes a memory cell array storing e-fuse data, a read-out control circuit reading e-fuse data in response to a read signal, a first internal pad receiving a first control signal, a read-out controller generating the read signal to define a read period, and to generate a second control signal following the read period, and a second internal pad receiving the second control signal, wherein the plurality of memory chips is connected series and each respective read-out control circuit and read-out controller in each one of the plurality of memory chips cooperate to implement a sequential read of e-fuse data across the plurality of memory chips.

摘要翻译： 公开了具有多个存储器芯片的多芯片封装。 每个存储器芯片包括存储电子熔丝数据的存储单元阵列，响应于读取信号读取电子熔丝数据的读出控制电路，接收第一控制信号的第一内部焊盘，产生读取的读出控制器的读出控制器 信号以定义读周期，并产生跟随读周期的第二控制信号，以及第二内部焊盘接收第二控制信号，其中多个存储器芯片连接串联，每个相应的读出控制电路和读 - 多个存储器芯片中的每一个的输出控制器协作以实现跨多个存储器芯片的电子熔丝数据的顺序读取。

公开(公告)号：US07701235B2

公开(公告)日：2010-04-20

申请号：US12098778

申请日：2008-04-07

申请人： Chang-Hyun Cho ,  Joon-Yeon Kim ,  Sang-Gu Kang ,  Sung-Mo Kang ,  Sang-Kyu Yoo

发明人： Chang-Hyun Cho ,  Joon-Yeon Kim ,  Sang-Gu Kang ,  Sung-Mo Kang ,  Sang-Kyu Yoo

IPC分类号： G01R31/02

CPC分类号： G01R31/2889 ,  G01R31/2891

摘要： Substrate test probing equipment having a force-receiving pattern for a probe card and a forcing part for a test head, and methods of using the same, in which with the force-receiving pattern for the probe card and the forcing part for the test head, thermal expansion and contraction of the probe card can be suppressed when the semiconductor substrate is being tested at high and low temperatures. To this end, to substrate test probing equipment having a substrate mover, a probe card, and a test head is prepared, in which the test head has a forcing part and the probe card has a force-receiving plate. A semiconductor substrate is placed on the substrate mover to be electrically connected with the probe card. The semiconductor substrate is electrically tested by the probe card and the test head. When the semiconductor substrate is being tested, the forcing part of the test head is brought into contact with the force-receiving pattern of the probe card.

摘要翻译： 具有用于探针卡的力接收图案和用于测试头的强制部件的基板测试探测设备及其使用方法，其中用于探针卡的受力图案和用于测试头的强制部件 当在高温和低温下测试半导体衬底时，可以抑制探针卡的热膨胀和收缩。 为此，制备具有基板移动器，探针卡和测试头的基板测试探测设备，其中测试头具有强制部分，探针卡具有受力板。 将半导体衬底放置在衬底移动器上以与探针卡电连接。 半导体衬底由探针卡和测试头电测试。 当半导体衬底被测试时，测试头的强制部分与探针卡的受力图案接触。

公开(公告)号：US07561467B2

公开(公告)日：2009-07-14

申请号：US11657697

申请日：2007-01-25

申请人： Dong-Ku Kang ,  Young-Ho Lim ,  Sang-Gu Kang

发明人： Dong-Ku Kang ,  Young-Ho Lim ,  Sang-Gu Kang

IPC分类号： G11C11/34

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643

摘要： A method is for programming a flash memory device which includes a plurality of memory cells storing multi-bit data representing one of a plurality of states. The method includes programming the multi-bit data into selected memory cells of the plurality of memory cells, the programming including a first verify-reading operation performed by a first verifying voltage, determining whether to execute a reprogramming operation for each of the selected memory cells, and reprogramming the selected memory cells in accordance with the determination. The reprogramming of the selected memory cells includes a second verify-reading operation performed by a second verifying voltage, the second verifying voltage being higher than the first verifying voltage.

摘要翻译： 一种用于对闪速存储器件进行编程的方法，该闪存器件包括存储表示多种状态之一的多位数据的多个存储器单元。 该方法包括将多位数据编程到多个存储单元的选定存储单元中，该程序包括由第一验证电压执行的第一验证读取操作，确定是否对所选存储单元中的每一个执行重编程操作 ，并且根据该确定重新编程所选择的存储单元。 所选择的存储单元的重新编程包括由第二验证电压执行的第二验证读取操作，第二验证电压高于第一验证电压。

公开(公告)号：US20080068883A1

公开(公告)日：2008-03-20

申请号：US11651521

申请日：2007-01-10

申请人： Sang-Gu Kang ,  Young-Ho Lim

发明人： Sang-Gu Kang ,  Young-Ho Lim

IPC分类号： G11C16/04

CPC分类号： G11C11/5628

摘要： Flash memory devices and methods of programming the same are provided. The flash memory devices include a plurality of memory cells storing multi-bit data representing at least one of first through fourth states and including most significant bits and least significant bits. The method includes programming the plural memory cells into a provisional state according to the least significant bit, and programming the plurality of memory cells into the second through fourth states from the first and provisional states according to the most significant bit. Programming the plurality of memory cells into the second through fourth states includes simultaneously programming the plurality of memory cells at least partially into at least two states during one programming operation period.

摘要翻译： 提供闪存设备及其编程方法。 闪速存储器件包括存储多位数据的多个存储单元，该多位数据表示第一至第四状态中的至少一个，并且包括最高有效位和最低有效位。 该方法包括根据最低有效位将多个存储器单元编程为临时状态，并根据最高有效位将第一至暂态状态的多个存储单元编程为第二至第四状态。 将多个存储器单元编程为第二至第四状态包括在一个编程操作周期期间至少部分地将多个存储器单元编程为至少两个状态。

公开(公告)号：US08154929B2

公开(公告)日：2012-04-10

申请号：US12481630

申请日：2009-06-10

申请人： Sang-Gu Kang

发明人： Sang-Gu Kang

IPC分类号： G11C11/34

CPC分类号： G11C7/02 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642

摘要： Disclosed is a flash memory device and a program-verify method. The flash memory device includes; a plurality of memory cells connected between a bit line and a common source line, and a data input/output circuit connected to the bit line and configured to store program data for a selected one of the plurality memory cells. The data input/output circuit maintains the program data during a program-verify operation and controls a voltage level on the bit line in accordance with the program data.

摘要翻译： 公开了一种闪存装置和程序验证方法。 闪存装置包括： 连接在位线和公共源极线之间的多个存储单元，以及数据输入/输出电路，连接到所述位线并且被配置为存储所述多个存储单元中所选择的一个的程序数据。 数据输入/输出电路在程序验证操作期间保持程序数据，并根据程序数据控制位线上的电压电平。

公开(公告)号：US20090180317A1

公开(公告)日：2009-07-16

申请号：US12416477

申请日：2009-04-01

申请人： Hee-Soo Kang ,  Dong-Uk Choi ,  Choong-Ho Lee ,  Sang-Gu Kang

发明人： Hee-Soo Kang ,  Dong-Uk Choi ,  Choong-Ho Lee ,  Sang-Gu Kang

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483

摘要： A non-volatile memory device includes a selection transistor coupled to a bit line. The device also includes a plurality of memory cells serially coupled to the selection transistor and at least one dummy cell located between the plurality of memory cells. The dummy cell is turned off during a programming operation of a memory cell located between the dummy cell and the selection transistor.

摘要翻译： 非挥发性存储器件包括耦合到位线的选择晶体管。 该装置还包括串联耦合到选择晶体管的多个存储单元和位于多个存储单元之间的至少一个虚拟单元。 在位于虚设单元和选择晶体管之间的存储单元的编程操作期间，虚设单元关闭。