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    Flash memory device reducing noise of common source line, program verify method thereof, and memory system including the same
    2.
    发明授权
    Flash memory device reducing noise of common source line, program verify method thereof, and memory system including the same 有权
    闪存器件降低公共源极线的噪声，其程序验证方法和包括其的存储器系统

    公开(公告)号：US08054692B2

    公开(公告)日：2011-11-08

    申请号：US12472639

    申请日：2009-05-27

    Applicant: Sang-gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

    Inventor： Sang-gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

    IPC: G11C11/34 ,  G11C16/06

    CPC classification number: G11C7/02 ,  G11C7/1048 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642

    Abstract: A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be programmed in a selected memory cell of the plurality of memory cells. The data input/output circuit maintains data to be programmed within the data input/output circuit during a program verify operation, and decreases noise in the common source line by selectively precharging the bit line based on the data to be programmed.

    Abstract translation: 闪存器件控制公共源极线电压并执行程序验证方法。 多个存储单元连接在位线和公共源极线之间。 数据输入/输出电路连接到位线，并且被配置为存储要编程在多个存储器单元的所选存储单元中的数据。 数据输入/输出电路在编程验证操作期间保持在数据输入/输出电路内编程的数据，并且通过基于要编程的数据选择性地预充电位线来降低公共源极线中的噪声。

    NON-VOLATILE MEMORY DEVICE
    3.
    发明申请
    NON-VOLATILE MEMORY DEVICE 失效
    非易失性存储器件

    公开(公告)号：US20100220535A1

    公开(公告)日：2010-09-02

    申请号：US12713219

    申请日：2010-02-26

    Applicant: Sang-Gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

    Inventor： Sang-Gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

    IPC: G11C5/14 ,  G11C7/00

    CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C16/24 ,  G11C2207/005

    Abstract: A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced.

    Abstract translation: 非易失性存储器件包括反馈电路和预充电开关晶体管。 反馈电路在预充电操作期间基于位线的电压电平产生反馈信号。 响应于反馈信号，预充电开关晶体管控制用于预充电位线的预充电电流。 可以增加预充电操作的速度和/或可以减少对多个位线进行预充电的偏置信号的失配。

    Non-volatile memory device
    4.
    发明授权
    Non-volatile memory device 失效
    非易失性存储器件

    公开(公告)号：US08243530B2

    公开(公告)日：2012-08-14

    申请号：US12713219

    申请日：2010-02-26

    Applicant: Sang-Gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

    Inventor： Sang-Gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

    IPC: G11C5/14 ,  G11C7/00

    CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C16/24 ,  G11C2207/005

    Abstract: A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced.

    Abstract translation: 非易失性存储器件包括反馈电路和预充电开关晶体管。 反馈电路在预充电操作期间基于位线的电压电平产生反馈信号。 响应于反馈信号，预充电开关晶体管控制用于预充电位线的预充电电流。 可以增加预充电操作的速度和/或可以减少对多个位线进行预充电的偏置信号的失配。

    FLASH MEMORY DEVICE REDUCING NOISE OF COMMON SOURCE LINE, PROGRAM VERIFY METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME
    6.
    发明申请
    FLASH MEMORY DEVICE REDUCING NOISE OF COMMON SOURCE LINE, PROGRAM VERIFY METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME 有权
    闪存存储器件减少通用源线的噪声，程序验证方法和包括其的存储器系统

    公开(公告)号：US20100002507A1

    公开(公告)日：2010-01-07

    申请号：US12472639

    申请日：2009-05-27

    Applicant: Sang-gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

    Inventor： Sang-gu Kang ,  Hee-Won Lee ,  Ju-Seok Lee ,  Jung-Ho Song

    IPC: G11C16/04 ,  G11C16/06 ,  G11C7/10

    CPC classification number: G11C7/02 ,  G11C7/1048 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642

    Abstract: A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be programmed in a selected memory cell of the plurality of memory cells. The data input/output circuit maintains data to be programmed within the data input/output circuit during a program verify operation, and decreases noise in the common source line by selectively precharging the bit line based on the data to be programmed.

    Abstract translation: 闪存器件控制公共源极线电压并执行程序验证方法。 多个存储单元连接在位线和公共源极线之间。 数据输入/输出电路连接到位线，并且被配置为存储要编程在多个存储器单元的所选存储单元中的数据。 数据输入/输出电路在编程验证操作期间保持在数据输入/输出电路内编程的数据，并且通过基于要编程的数据选择性地预充电位线来降低公共源极线中的噪声。

    OPTICAL COUPLER AND ACTIVE OPTICAL MODULE COMPRISING THE SAME
    7.
    发明申请
    OPTICAL COUPLER AND ACTIVE OPTICAL MODULE COMPRISING THE SAME 审中-公开
    光耦合器和包含该光耦合器的主动光学模块

    公开(公告)号：US20110141758A1

    公开(公告)日：2011-06-16

    申请号：US12949447

    申请日：2010-11-18

    Applicant: Hong-Seok SEO ,  Joon Tae Ahn ,  Bong Je Park ,  Dae Kon Oh ,  Jung-Ho Song

    Inventor： Hong-Seok SEO ,  Joon Tae Ahn ,  Bong Je Park ,  Dae Kon Oh ,  Jung-Ho Song

    IPC: H01S3/00 ,  G02B6/26

    CPC classification number: H01S3/094019 ,  G02B6/4214 ,  H01S3/0675 ,  H01S3/094007 ,  H01S3/0941 ,  H01S3/11

    Abstract: Provided are an optical coupler, which can improve miniaturization and integration, and an active optical module comprising the same. The optical coupler comprises a hollow optical block having a through hole formed to pass an optical fiber therethrough. The hollow optical block comprises at least one incidence plane, at least one internal reflection plane, and at least one tapering region. The incidence plane is disposed at the bottom of the hollow optical block, which is parallel to the through hole, to incident-transmit light. The internal reflection plane is disposed at the top of the hollow optical block, which is opposite to the incidence plane, to reflect the light, which is received from the incidence plane, into the hollow optical block. The tapering region is configured to concentrate the light on the optical fiber in the through hole. The tapering region is formed such that the outer diameter of the hollow optical block decreases away from the internal reflection plane and the incidence plane.

    Abstract translation: 提供了可以改善小型化和集成的光耦合器，以及包括该光耦合器的有源光学模块。 光耦合器包括中空的光学块，该中空光学块具有形成为使光纤通过的通孔。 中空光学块包括至少一个入射平面，至少一个内部反射平面和至少一个锥形区域。 入射平面设置在平行于通孔的中空光学块的底部入射透射光。 内反射面设置在与入射面相反的中空光学块的顶部，以将从入射平面接收的光反射到中空光学块中。 锥形区域被配置为将光聚集在通孔中的光纤上。 锥形区域形成为使得中空光学块的外径从内反射面和入射面减小。

    System and method for accessing node of private network
    8.
    发明授权
    System and method for accessing node of private network 有权
    用于接入私网节点的系统和方法

    公开(公告)号：US07221671B2

    公开(公告)日：2007-05-22

    申请号：US09901486

    申请日：2001-07-10

    Applicant: Min-Seop Jeong ,  Jung-Ho Song

    Inventor： Min-Seop Jeong ,  Jung-Ho Song

    IPC: H04L12/66

    CPC classification number: H04L61/2514 ,  H04L29/12009 ,  H04L29/12367 ,  H04L29/12377 ,  H04L29/12924 ,  H04L61/2517 ,  H04L61/6063

    Abstract: A system for accessing a node of a private network includes an assigning portion for assigning external port values to respective network nodes based on information collected from the network nodes of the private network, and storing the assigned external port values; an exchanging portion for exchanging the external port values of the respective network nodes of private networks; and an address converting portion for converting the external port values into corresponding private IP addresses and internal port values when a network node of one private network accesses another network node of another private network by using the external port values of another network node of another private network. Accordingly, a network node of a private network without a global IP address becomes accessible.

    Abstract translation: 用于访问私有网络的节点的系统包括：分配部分，用于基于从专用网络的网络节点收集的信息将外部端口值分配给各个网络节点，并存储所分配的外部端口值; 用于交换专用网络的各个网络节点的外部端口值的交换部分; 以及地址转换部分，当一个专用网络的网络节点通过使用另一个专用网络的另一个网络节点的外部端口值来访问另一个专用网络的另一个网络节点时，将外部端口值转换为相应的专用IP地址和内部端口值 。 因此，没有全局IP地址的专用网络的网络节点变得可访问。

    Methods of programming multi-level cell nonvolatile memory devices and devices so operating
    9.
    发明授权
    Methods of programming multi-level cell nonvolatile memory devices and devices so operating 有权
    编程多级单元非易失性存储器件和器件的操作方法

    公开(公告)号：US09343158B2

    公开(公告)日：2016-05-17

    申请号：US14165835

    申请日：2014-01-28

    Applicant: Jung-Ho Song ,  Su-Yong Kim ,  Sang-Won Hwang

    Inventor： Jung-Ho Song ,  Su-Yong Kim ,  Sang-Won Hwang

    IPC: G11C11/34 ,  G11C16/14 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3459

    Abstract: To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.

    Abstract translation: 在非易失性存储器件中编程包括通过至少两个程序步骤被编程成多个状态的多个存储器单元，相对于耦合到所选择的存储单元，从擦除电平到第一目标电平执行主程序 字线相对于耦合到所选择的字线的存储器单元与原始程序相关联地从擦除电平执行预编程电平，其中预编程电平大于擦除电平并小于第一目标电平 相对于耦合到所选字线的预编程存储器单元，从预编程级到第二目标级执行次程序。

    Nonvolatile memory device and method of reading data in nonvolatile memory device
    10.
    发明授权
    Nonvolatile memory device and method of reading data in nonvolatile memory device 有权
    非易失性存储器件和非易失性存储器件中的数据读取方法

    公开(公告)号：US08760919B2

    公开(公告)日：2014-06-24

    申请号：US13598892

    申请日：2012-08-30

    Applicant: Jung-Ho Song ,  Jin-Yub Lee ,  Jae-Woo Im ,  Seung-Jae Lee ,  Sang-So Park

    Inventor： Jung-Ho Song ,  Jin-Yub Lee ,  Jae-Woo Im ,  Seung-Jae Lee ,  Sang-So Park

    IPC: G11C11/56 ,  G11C16/04

    CPC classification number: G11C11/56 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3404 ,  G11C2211/56

    Abstract: A method is provided for reading data in a nonvolatile memory device. The method includes performing a first read operation on multiple multi-level memory cells (MLCs), performing a first sensing operation on at least one flag cell corresponding to the MLCs, selectively performing a second read operation on the MLCs based on a result of the first sensing operation, and performing a second sensing operation on the at least one flag cell when the second read operation is performed. Read data is output based on results of the first read operation and the first sensing operation when the second read operation is not performed, and the read data is output based on result of the first read operation, the first sensing operation, the second read operation and the second sensing operation when the second read operation is performed. The read data corresponds to programmed data in the MLCs.

    Abstract translation: 提供了一种用于在非易失性存储器件中读取数据的方法。 该方法包括：对多个多电平存储器单元（MLC），在对应于MLC中的至少一个标志单元，基于所述结果选择性地执行上的MLC的第二读取操作执行第一读出操作的第一次读操作 第一感测操作，并且当执行第二读取操作时对所述至少一个标志单元执行第二感测操作。 在不执行第二读取操作时，基于第一读取操作和第一感测操作的结果输出读取数据，并且基于第一读取操作，第一感测操作，第二读取操作的结果来输出读取数据 以及执行第二读取操作时的第二感测操作。 读取数据对应于MLC中的编程数据。

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