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公开(公告)号：US09007345B2
公开(公告)日：2015-04-14
申请号：US13413189
申请日：2012-03-06
Applicant: Young-ran Han , Hee-won Lee , Kyoung-oh Choi
Inventor： Young-ran Han , Hee-won Lee , Kyoung-oh Choi
CPC classification number: G06F3/041 , G06F3/042 , G06F2203/04104 , G06F2203/04106
Abstract: A method and apparatus for displaying an object are provided. The display apparatus includes a display unit which displays an object, a first touch sensing unit which senses a user input by a first input method, a second touch sensing unit which senses a user input by a second input method, a coordinate calculation unit which calculates coordinate values sensed by the first and the second touch sensing units, and a controller which, in response to a user input being simultaneously sensed by the first and the second touch sensing units, compares the coordinate values sensed by the first and the second touch sensing units and determines whether the user input is a single touch input or a multi-touch input, and, according to a result of the determination, controls to display the object on the display unit.
Abstract translation: 提供了一种用于显示对象的方法和装置。 显示装置包括显示对象的显示单元，通过第一输入方法感测用户输入的第一触摸感测单元，通过第二输入方法感测用户输入的第二触摸感测单元，计算用户输入的坐标计算单元 由第一和第二触摸感测单元感测的坐标值，以及响应于由第一和第二触摸感测单元同时感测的用户输入的控制器，比较由第一和第二触摸感测感测到的坐标值 单元，并且确定用户输入是单触式输入还是多触摸输入，并且根据确定结果控制在显示单元上显示对象。
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公开(公告)号：US20090296482A1
公开(公告)日：2009-12-03
申请号：US12461317
申请日：2009-08-07
Applicant: Dong-Ku Kang , Hee-Won Lee
Inventor： Dong-Ku Kang , Hee-Won Lee
IPC: G11C16/04
CPC classification number: G11C16/10 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C2211/5642
Abstract: In one embodiment, the non-volatile memory device includes a plurality of normal memory cells, and at least one flag memory cell associated with one of the plurality of normal memory cells. A normal page buffer is configured to store data read from one of the plurality of normal memory cells. The normal page buffer includes a main latch storing the read data. A control circuit is configured to selectively change data stored in the main latch during a read operation based on a state of the flag memory cell.
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公开(公告)号：US07589998B2
公开(公告)日：2009-09-15
申请号：US11651990
申请日：2007-01-11
Applicant: Dong-Ku Kang , Hee-Won Lee
Inventor： Dong-Ku Kang , Hee-Won Lee
CPC classification number: G11C16/10 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C2211/5642
Abstract: In one embodiment, the non-volatile memory device includes a plurality of normal memory cells, and at least one flag memory cell associated with one of the plurality of normal memory cells. A normal page buffer is configured to store data read from one of the plurality of normal memory cells. The normal page buffer includes a main latch storing the read data. A control circuit is configured to selectively change data stored in the main latch during a read operation based on a state of the flag memory cell.
Abstract translation: 在一个实施例中，非易失性存储器件包括多个正常存储器单元，以及至少一个与多个正常存储器单元之一相关联的标志存储单元。 正常页面缓冲器被配置为存储从多个正常存储器单元之一读取的数据。 正常页面缓冲器包括存储读取数据的主锁存器。 控制电路被配置为基于标志存储器单元的状态来选择性地改变在读取操作期间存储在主锁存器中的数据。
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4.发明申请Voltage reset circuits for a semiconductor memory device using option fuse circuit and methods of resetting the same 失效使用选项保险丝电路的半导体存储器件的电压复位电路及其复位方法公开(公告)号：US20070183245A1
公开(公告)日：2007-08-09
申请号：US11642105
申请日：2006-12-20
Applicant: Hee-Won Lee , Dae-Seok Byeon , Wook-Ghee Hahn
Inventor： Hee-Won Lee , Dae-Seok Byeon , Wook-Ghee Hahn
IPC: G11C17/18
CPC classification number: G11C16/30 , G11C5/147 , G11C16/04 , G11C17/18 , G11C29/02 , G11C29/021 , G11C29/028
Abstract: Control circuits for a voltage regulator of a semiconductor memory device include an option fuse circuit and a fusing control circuit. The option fuse circuit includes a plurality of fuses and a selection circuit that selects one of the plurality of fuses responsive to a control signal. An output voltage associated with the voltage reset circuit is adjusted responsive to a state of the selected one of the plurality of fuses. A fusing control circuit generates the control signal to allow multiple adjustments of the output voltage by the voltage reset circuit. The option fuse circuit may be a plurality of option fuse circuits and the output voltage may be adjusted responsive to the states of the respective selected ones of the plurality of fuses of the option fuse circuits.
Abstract translation: 用于半导体存储器件的电压调节器的控制电路包括选件熔丝电路和定影控制电路。 选项熔丝电路包括多个保险丝和选择电路，其根据控制信号选择多个保险丝之一。 响应于所选择的多个保险丝的状态来调整与电压复位电路相关联的输出电压。 熔断控制电路产生控制信号以允许电压复位电路对输出电压进行多次调节。 选项保险丝电路可以是多个选项保险丝电路，并且可以响应于选项保险丝电路的多个保险丝中的相应选择的保险丝的状态来调整输出电压。
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5.发明授权Flash memory device reducing noise of common source line, program verify method thereof, and memory system including the same 有权闪存器件降低公共源极线的噪声，其程序验证方法和包括其的存储器系统公开(公告)号：US08054692B2
公开(公告)日：2011-11-08
申请号：US12472639
申请日：2009-05-27
Applicant: Sang-gu Kang , Hee-Won Lee , Ju-Seok Lee , Jung-Ho Song
Inventor： Sang-gu Kang , Hee-Won Lee , Ju-Seok Lee , Jung-Ho Song
CPC classification number: G11C7/02 , G11C7/1048 , G11C11/5628 , G11C16/0483 , G11C2211/5621 , G11C2211/5642
Abstract: A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be programmed in a selected memory cell of the plurality of memory cells. The data input/output circuit maintains data to be programmed within the data input/output circuit during a program verify operation, and decreases noise in the common source line by selectively precharging the bit line based on the data to be programmed.
Abstract translation: 闪存器件控制公共源极线电压并执行程序验证方法。 多个存储单元连接在位线和公共源极线之间。 数据输入/输出电路连接到位线，并且被配置为存储要编程在多个存储器单元的所选存储单元中的数据。 数据输入/输出电路在编程验证操作期间保持在数据输入/输出电路内编程的数据，并且通过基于要编程的数据选择性地预充电位线来降低公共源极线中的噪声。
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Patent Agency Ranking
公开(公告)号：US20100220535A1
公开(公告)日：2010-09-02
申请号：US12713219
申请日：2010-02-26
Applicant: Sang-Gu Kang , Hee-Won Lee , Ju-Seok Lee , Jung-Ho Song
Inventor： Sang-Gu Kang , Hee-Won Lee , Ju-Seok Lee , Jung-Ho Song
CPC classification number: G11C7/12 , G11C5/147 , G11C16/24 , G11C2207/005
Abstract: A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced.
Abstract translation: 非易失性存储器件包括反馈电路和预充电开关晶体管。 反馈电路在预充电操作期间基于位线的电压电平产生反馈信号。 响应于反馈信号，预充电开关晶体管控制用于预充电位线的预充电电流。 可以增加预充电操作的速度和/或可以减少对多个位线进行预充电的偏置信号的失配。
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7.发明授权Systems and methods for performing a program-verify process on a nonvolatile memory by selectively pre-charging bit lines associated with memory cells during the verify operations 有权用于通过在验证操作期间选择性地预充电与存储器单元相关联的位线来对非易失性存储器执行程序验证过程的系统和方法公开(公告)号：US08068361B2
公开(公告)日：2011-11-29
申请号：US12533720
申请日：2009-07-31
Applicant: Sang-Gu Kang , Hee-won Lee , Ju Seok Lee , Jung-Ho Song
Inventor： Sang-Gu Kang , Hee-won Lee , Ju Seok Lee , Jung-Ho Song
IPC: G11C16/04
CPC classification number: G11C16/24 , G11C11/5628 , G11C16/3454 , G11C2211/5621
Abstract: A nonvolatile memory system is operated by performing a program loop on each of a plurality of memory cells, each program loop comprising at least one program-verify operation and selectively pre-charging bit lines associated with each of the plurality of memory cells during the at least one program-verify operation.
Abstract translation: 通过在多个存储器单元中的每一个上执行程序循环来操作非易失性存储器系统，每个程序循环包括至少一个程序验证操作，并且在at期间选择性地预充电与多个存储器单元中的每一个相关联的位线 至少一个程序验证操作。
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公开(公告)号：US20070171711A1
公开(公告)日：2007-07-26
申请号：US11651990
申请日：2007-01-11
Applicant: Dong-Ku Kang , Hee-Won Lee
Inventor： Dong-Ku Kang , Hee-Won Lee
CPC classification number: G11C16/10 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C2211/5642
Abstract: In one embodiment, the non-volatile memory device includes a plurality of normal memory cells, and at least one flag memory cell associated with one of the plurality of normal memory cells. A normal page buffer is configured to store data read from one of the plurality of normal memory cells. The normal page buffer includes a main latch storing the read data. A control circuit is configured to selectively change data stored in the main latch during a read operation based on a state of the flag memory cell.
Abstract translation: 在一个实施例中，非易失性存储器件包括多个正常存储器单元，以及至少一个与多个正常存储器单元之一相关联的标志存储单元。 正常页面缓冲器被配置为存储从多个正常存储器单元之一读取的数据。 正常页面缓冲器包括存储读取数据的主锁存器。 控制电路被配置为基于标志存储器单元的状态来选择性地改变在读取操作期间存储在主锁存器中的数据。
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公开(公告)号：US20180040362A1
公开(公告)日：2018-02-08
申请号：US15604406
申请日：2017-05-24
Applicant: Dong-Hun KWAK , Hee-Woong KANG , Jun-Ho SEO , Hee-Won LEE
Inventor： Dong-Hun KWAK , Hee-Woong KANG , Jun-Ho SEO , Hee-Won LEE
IPC: G11C11/4074 , G11C16/30 , G11C16/06 , G11C11/408 , G11C16/34 , G11C11/56 , G11C11/4097 , G11C16/04 , G11C16/10
CPC classification number: G11C11/4074 , G11C7/109 , G11C7/12 , G11C8/12 , G11C11/4082 , G11C11/4085 , G11C11/4097 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/30 , G11C16/3436 , G11C2207/2209
Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.
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公开(公告)号：US08243530B2
公开(公告)日：2012-08-14
申请号：US12713219
申请日：2010-02-26
Applicant: Sang-Gu Kang , Hee-Won Lee , Ju-Seok Lee , Jung-Ho Song
Inventor： Sang-Gu Kang , Hee-Won Lee , Ju-Seok Lee , Jung-Ho Song
CPC classification number: G11C7/12 , G11C5/147 , G11C16/24 , G11C2207/005
Abstract: A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced.
Abstract translation: 非易失性存储器件包括反馈电路和预充电开关晶体管。 反馈电路在预充电操作期间基于位线的电压电平产生反馈信号。 响应于反馈信号，预充电开关晶体管控制用于预充电位线的预充电电流。 可以增加预充电操作的速度和/或可以减少对多个位线进行预充电的偏置信号的失配。
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