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1.发明申请FLASH MEMORY DEVICE REDUCING NOISE OF COMMON SOURCE LINE, PROGRAM VERIFY METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME 有权闪存存储器件减少通用源线的噪声，程序验证方法和包括其的存储器系统公开(公告)号：US20100002507A1
公开(公告)日：2010-01-07
申请号：US12472639
申请日：2009-05-27
Applicant: Sang-gu Kang , Hee-Won Lee , Ju-Seok Lee , Jung-Ho Song
Inventor： Sang-gu Kang , Hee-Won Lee , Ju-Seok Lee , Jung-Ho Song
CPC classification number: G11C7/02 , G11C7/1048 , G11C11/5628 , G11C16/0483 , G11C2211/5621 , G11C2211/5642
Abstract: A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be programmed in a selected memory cell of the plurality of memory cells. The data input/output circuit maintains data to be programmed within the data input/output circuit during a program verify operation, and decreases noise in the common source line by selectively precharging the bit line based on the data to be programmed.
Abstract translation: 闪存器件控制公共源极线电压并执行程序验证方法。 多个存储单元连接在位线和公共源极线之间。 数据输入/输出电路连接到位线，并且被配置为存储要编程在多个存储器单元的所选存储单元中的数据。 数据输入/输出电路在编程验证操作期间保持在数据输入/输出电路内编程的数据，并且通过基于要编程的数据选择性地预充电位线来降低公共源极线中的噪声。
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2.发明授权Flash memory device reducing noise of common source line, program verify method thereof, and memory system including the same 有权闪存器件降低公共源极线的噪声，其程序验证方法和包括其的存储器系统公开(公告)号：US08054692B2
公开(公告)日：2011-11-08
申请号：US12472639
申请日：2009-05-27
Applicant: Sang-gu Kang , Hee-Won Lee , Ju-Seok Lee , Jung-Ho Song
Inventor： Sang-gu Kang , Hee-Won Lee , Ju-Seok Lee , Jung-Ho Song
CPC classification number: G11C7/02 , G11C7/1048 , G11C11/5628 , G11C16/0483 , G11C2211/5621 , G11C2211/5642
Abstract: A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be programmed in a selected memory cell of the plurality of memory cells. The data input/output circuit maintains data to be programmed within the data input/output circuit during a program verify operation, and decreases noise in the common source line by selectively precharging the bit line based on the data to be programmed.
Abstract translation: 闪存器件控制公共源极线电压并执行程序验证方法。 多个存储单元连接在位线和公共源极线之间。 数据输入/输出电路连接到位线，并且被配置为存储要编程在多个存储器单元的所选存储单元中的数据。 数据输入/输出电路在编程验证操作期间保持在数据输入/输出电路内编程的数据，并且通过基于要编程的数据选择性地预充电位线来降低公共源极线中的噪声。
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公开(公告)号：US08149620B2
公开(公告)日：2012-04-03
申请号：US12395730
申请日：2009-03-02
Applicant: Sang-gu Kang
Inventor： Sang-gu Kang
IPC: G11C16/04
CPC classification number: G11C11/5621 , G11C16/0483
Abstract: A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells.
Abstract translation: 非易失性半导体存储器件包括耦合到位线的串选择晶体管。 该装置还包括串联耦合到串选择晶体管的多个存储单元，其中至少一个存储单元被配置为在多个存储单元的擦除过程期间处于编程状态。
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公开(公告)号：US08520434B2
公开(公告)日：2013-08-27
申请号：US13198241
申请日：2011-08-04
Applicant: Sang-gu Kang , Young-ho Lim
Inventor： Sang-gu Kang , Young-ho Lim
Abstract: Provided is a method of storing configuration data regarding an operating environment of a flash memory device, which includes a memory cell array having an electrical fuse (E-Fuse) block for storing the configuration data. The method includes storing the configuration data in multiple strings of the E-Fuse block, each string including multiple memory cells configured to store one bit.
Abstract translation: 提供一种存储关于闪速存储器件的操作环境的配置数据的方法，其包括具有用于存储配置数据的电熔丝（E-Fuse）块的存储单元阵列。 该方法包括将配置数据存储在E-Fuse块的多个串中，每个串包括被配置为存储一位的多个存储单元。
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公开(公告)号：US07826269B2
公开(公告)日：2010-11-02
申请号：US12052003
申请日：2008-03-20
Applicant: Sang-gu Kang
Inventor： Sang-gu Kang
IPC: G11C11/34
CPC classification number: G11C29/027 , G11C16/0483 , G11C29/82 , G11C2029/4402
Abstract: Provided are a flash memory device and a method of driving the same for improving reliability of stored set information. The method of driving the flash memory device includes applying power to the flash memory device, the flash memory device having a memory cell array for storing set information regarding operation environment settings, where the set information includes at least one bit. The method further includes performing an initial read operation on the memory cell array and judging a status of data, corresponding to the set information, read during the initial read operation to determine whether the initial read operation has passed or failed. Each bit of the set information is extended to n bits (where n is an integer equal to or greater than 2). The n bits are respectively stored in different input/output regions in the memory cell array.
Abstract translation: 提供了一种闪存装置及其驱动方法，用于提高存储的集信息的可靠性。 驱动闪速存储装置的方法包括向闪存装置施加电力，闪速存储装置具有用于存储关于操作环境设置的设置信息的存储单元阵列，其中所述设置信息包括至少一个位。 该方法还包括对存储单元阵列执行初始读取操作，并且在初始读取操作期间判断对应于所设置的信息的数据的状态，以确定初始读取操作是否已经通过或失败。 设置信息的每一位被扩展为n位（其中n是等于或大于2的整数）。 n位分别存储在存储单元阵列中的不同输入/输出区域中。
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Patent Agency Ranking
6.发明申请Multi probe card unit, probe test device including the multi probe card unit, and methods of fabricating and using the same 审中-公开多探针卡单元，包括多探针卡单元的探针测试装置及其制造和使用方法公开(公告)号：US20080297185A1
公开(公告)日：2008-12-04
申请号：US12155185
申请日：2008-05-30
Applicant: Sang-gu Kang , Chang-Hyun Cho , Sung-mo Kang , Sang-kyo Yoo , Joon-yeon Kim
Inventor： Sang-gu Kang , Chang-Hyun Cho , Sung-mo Kang , Sang-kyo Yoo , Joon-yeon Kim
CPC classification number: G01R1/07314 , G01R31/2891 , Y10T29/49222
Abstract: A multi probe card unit, a probe test device including the multi probe card unit, and methods of fabricating and using the same are provided. The multi probe card unit may include at least one probe card including a first plurality of probes on a first surface of the at least one probe card and a second plurality of probes on a second surface of the at least one probe card.
Abstract translation: 提供了多探针卡单元，包括多探针卡单元的探针测试装置及其制造和使用方法。 多探针卡单元可以包括至少一个探针卡，其包括在所述至少一个探针卡的第一表面上的第一多个探针和在所述至少一个探针卡的第二表面上的第二多个探针。
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公开(公告)号：US20070159886A1
公开(公告)日：2007-07-12
申请号：US11523571
申请日：2006-09-20
Applicant: Sang-gu Kang
Inventor： Sang-gu Kang
IPC: G11C16/04
CPC classification number: G11C11/5621 , G11C16/0483
Abstract: A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells.
Abstract translation: 非易失性半导体存储器件包括耦合到位线的串选择晶体管。 该装置还包括串联耦合到串选择晶体管的多个存储单元，其中至少一个存储单元被配置为在多个存储单元的擦除过程期间处于编程状态。
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公开(公告)号：US08358544B2
公开(公告)日：2013-01-22
申请号：US13406837
申请日：2012-02-28
Applicant: Sang-gu Kang
Inventor： Sang-gu Kang
IPC: G11C16/04
CPC classification number: G11C11/5621 , G11C16/0483
Abstract: A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells.
Abstract translation: 非易失性半导体存储器件包括耦合到位线的串选择晶体管。 该装置还包括串联耦合到串选择晶体管的多个存储单元，其中至少一个存储单元被配置为在多个存储单元的擦除过程期间处于编程状态。
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9.发明授权Flash memory devices including ready/busy control circuits and methods of testing the same 有权闪存设备包括就绪/繁忙的控制电路和测试方法公开(公告)号：US08179732B2
公开(公告)日：2012-05-15
申请号：US12370227
申请日：2009-02-12
Applicant: Sang-gu Kang
Inventor： Sang-gu Kang
IPC: G11C7/00
CPC classification number: G11C29/44 , G11C7/1051 , G11C7/1063 , G11C16/04 , G11C2029/4402
Abstract: A flash memory device includes a chip disable fuse circuit that has a fuse and that outputs a chip disable signal when the fuse is cut out, and a ready/busy control circuit that forcibly activates a ready/busy signal representing an internal operational state in response to the chip disable signal and externally outputs the ready/busy signal through a ready/busy output pin.
Abstract translation: 闪存器件包括具有熔丝的片断禁止熔丝电路，并且当熔断器被切断时输出芯片禁止信号;以及就绪/忙控制电路，其强制地启动代表内部操作状态的就绪/忙信号 到芯片禁止信号，并通过就绪/忙碌输出引脚外部输出就绪/忙信号。
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10.发明申请Flash memory system compensating reduction in read margin between memory cell program states 有权闪存系统补偿了存储单元程序状态之间读取余量的减少公开(公告)号：US20070171722A1
公开(公告)日：2007-07-26
申请号：US11595925
申请日：2006-11-13
Applicant: Sang-gu Kang , Young-Ho Lim
Inventor： Sang-gu Kang , Young-Ho Lim
CPC classification number: G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3459
Abstract: A memory system includes a flash memory and a memory controller configured to control the flash memory. The memory controller determines whether program data provided from a host are all stored in the flash memory during a program operation. When the determination result is that the program data are all stored in the flash memory, the memory controller controls the flash memory to execute a dummy program operation for the next wordline of a final wordline in which the program data are stored.
Abstract translation: 存储器系统包括闪速存储器和被配置为控制闪速存储器的存储器控制器。 存储器控制器在程序操作期间确定从主机提供的程序数据是否全部存储在闪速存储器中。 当确定结果是程序数据全部存储在闪速存储器中时，存储器控制器控制闪存以对存储程序数据的最终字线的下一个字线执行虚拟程序操作。
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