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69 条记录 (耗时 0.022 秒)

    Semiconductor device and method of manufacturing the same
    21.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07994538B2

    公开(公告)日：2011-08-09

    申请号：US12205074

    申请日：2008-09-05

    申请人： Young Suk Kim

    发明人： Young Suk Kim

    IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

    CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

    摘要： A semiconductor device to which a stress technique is applied and in which a leakage current caused by silicidation can be suppressed. A gate electrode is formed over an element region defined by an isolation region formed in a semiconductor substrate with a gate insulating film between. Extension regions and source/drain regions are formed in the element region on both sides of the gate electrode. In addition, a semiconductor layer which differs from the semiconductor substrate in lattice constant is formed apart from at least part of the isolation region. By doing so, the formation of a spike near the isolation region is suppressed even if a silicide layer is formed. Accordingly, a leakage current caused by such a spike can be suppressed.

    摘要翻译： 应用技术的半导体器件可以抑制由硅化产生的漏电流。 栅极电极形成在由形成在半导体衬底中的隔离区限定的元件区域上，栅绝缘膜在其间。 延伸区域和源极/漏极区域形成在栅电极两侧的元件区域中。 此外，与晶格常数的半导体衬底不同的半导体层与隔离区域的至少一部分分开形成。 通过这样做，即使形成硅化物层，也抑制了隔离区附近的尖峰的形成。 因此，可以抑制由这种尖峰引起的漏电流。

    Semiconductor device with strained transistors and its manufacture
    22.
    发明授权
    Semiconductor device with strained transistors and its manufacture 有权
    具有应变晶体管的半导体器件及其制造

    公开(公告)号：US07985641B2

    公开(公告)日：2011-07-26

    申请号：US12434944

    申请日：2009-05-04

    申请人： Young Suk Kim ,  Yosuke Shimamune

    发明人： Young Suk Kim ,  Yosuke Shimamune

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and a p-channel field effect transistor formed in the semiconductor substrate and having p-type source/drain regions made of a third semiconductor material different from the first semiconductor material, wherein the second and third semiconductor materials are different materials. The semiconductor device having n- and p-channel transistors has improved performance by utilizing stress.

    摘要翻译： 半导体器件具有：由第一半导体材料制成的半导体衬底; n型沟道场效应晶体管，其形成在所述半导体衬底中并且具有由与所述第一半导体材料不同的第二半导体材料制成的n型源/漏区; 以及形成在所述半导体衬底中并具有由与所述第一半导体材料不同的第三半导体材料制成的p型源极/漏极区的p沟道场效应晶体管，其中所述第二和第三半导体材料是不同的材料。 具有n沟道晶体管和p沟道晶体管的半导体器件通过利用应力来提高性能。

    SURFACE EXPRESSION VECTOR FOR FUSION PROTEIN OF MYO-2 PEPTIDE MULTIMER AND MYOSTATIN, AND MICROORGANISM TRANSFORMED BY THEREOF
    23.
    发明申请
    SURFACE EXPRESSION VECTOR FOR FUSION PROTEIN OF MYO-2 PEPTIDE MULTIMER AND MYOSTATIN, AND MICROORGANISM TRANSFORMED BY THEREOF 有权
    MYO-2肽多糖和肌糖蛋白融合蛋白的表面表达载体及其转化的微生物

    公开(公告)号：US20100226891A1

    公开(公告)日：2010-09-09

    申请号：US12682453

    申请日：2007-11-30

    申请人： Moon-Hee Sung ,  Chul Joong Kim ,  Haryoung Poo ,  Ji Yeon Kim ,  Young Suk Kim ,  Long Chun Xu

    发明人： Moon-Hee Sung ,  Chul Joong Kim ,  Haryoung Poo ,  Ji Yeon Kim ,  Young Suk Kim ,  Long Chun Xu

    IPC分类号： A61K35/74 ,  C07K7/08 ,  C07K14/00 ,  C12N15/74 ,  C12N1/21 ,  A61K38/16 ,  A61P21/00 ,  A61P3/00

    CPC分类号： C07K14/475

    摘要： The present invention relates to a fusion protein in which a myostatin mature protein is fused to a multimer of myostatin-derived antigenic peptide Myo-2, a surface expression vector containing a polynucleotide encoding the fusion protein, a recombinant microorganism transformed with the vector, and a feedstuff additive or a pharmaceutical composition containing the microorganism as an effective ingredient. The feedstuff additive or pharmaceutical composition according to the present invention can be used for muscle development and regulation of muscle growth in livestock and poultry, as well as for preventing and treating muscle-wasting diseases and degenerative diseases such as muscular dystrophy, muscular atrophy and the like. In addition, the transformed strain shows the same effect even if the strain itself after culture thereof is directly used, and thus it is very economical.

    摘要翻译： 本发明涉及一种融合蛋白，其中肌生成抑制素成熟蛋白质与产生肌生成抑制素的抗原肽Myo-2的多聚体融合，含有编码融合蛋白的多核苷酸的表面表达载体，用载体转化的重组微生物，以及 饲料添加剂或含有该微生物作为有效成分的药物组合物。 根据本发明的饲料添加剂或药物组合物可用于肌肉发育和调节家畜和家禽中的肌肉生长，以及用于预防和治疗肌肉消瘦疾病和退行性疾病如肌营养不良症，肌肉萎缩症和 喜欢。 此外，即使直接使用其培养后的菌株本身，转化菌株也显示相同的效果，因此是非常经济的。

    Washing machine
    24.
    发明申请
    Washing machine 审中-公开
    洗衣机

    公开(公告)号：US20090308110A1

    公开(公告)日：2009-12-17

    申请号：US12453565

    申请日：2009-05-14

    申请人： Bon Kwon Koo ,  Deok Kyu Kim ,  Jae Hyuk Jang ,  Bo Sung Seo ,  Hyun Seok Seo ,  Young Suk Kim

    发明人： Bon Kwon Koo ,  Deok Kyu Kim ,  Jae Hyuk Jang ,  Bo Sung Seo ,  Hyun Seok Seo ,  Young Suk Kim

    IPC分类号： D06F35/00

    CPC分类号： D06F37/225

    摘要： A washing machine is provided. The washing machine controls a dehydration rotation speed by detecting a phase difference between a ball balancer and the laundry. Further, the washing machine controls a dehydration rotation speed at a dehydration segment based on a dehydration rotation speed of a driving device. Thereby, the washing machine minimizes energy using in a dehydration process by accelerating the dehydration rotation speed at a point at which a phase difference between the ball balancer and the laundry is a maximum. Further, by accelerating the dehydration rotation speed at a point at which the phase difference is a maximum, a vibration of the washing machine is remarkably reduced.

    摘要翻译： 提供洗衣机。 洗衣机通过检测球平衡器和衣物之间的相位差来控制脱水转速。 此外，洗衣机基于驱动装置的脱水转速来控制脱水段的脱水转速。 因此，洗衣机通过在球平衡器和衣物之间的相位差最大的点处加速脱水转速而使脱水过程中的能量最小化。 此外，通过在相位差最大的点加速脱水转速，洗衣机的振动显着降低。

    Circuit and Method for a Vdd Level Memory Sense Amplifier
    25.
    发明申请
    Circuit and Method for a Vdd Level Memory Sense Amplifier 有权
    用于Vdd级存储器检测放大器的电路和方法

    公开(公告)号：US20090231939A1

    公开(公告)日：2009-09-17

    申请号：US12046276

    申请日：2008-03-11

    申请人： Kuoyuan Peter Hsu ,  Young Suk Kim ,  Bing Wang ,  Ming Chieh Huang

    发明人： Kuoyuan Peter Hsu ,  Young Suk Kim ,  Bing Wang ,  Ming Chieh Huang

    IPC分类号： G11C7/08 ,  G11C7/12

    CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097

    摘要： A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense amplifier is coupled to the bit line and the complementary bit line. A control signal couples a reference voltage to the complementary bit line. A positive precharge voltage is applied to the bit line and complementary bit line prior to the sense amplifier being enabled. The memory cell outputs a voltage to the bit line responsive to a word line, and the sense amplifier senses the differential voltage between the bit line and the complementary bit line responsive to a sense enable signal. A voltage regulator for generating the reference voltage, preferably about 80% of a positive supply voltage, is disclosed. A method of sensing data stored by a memory cell is disclosed.

    摘要翻译： 公开了一种用于感测由存储器单元存储的电荷的读出放大器的电路和方法。 存储单元耦合到位线，互补位线和差分读出放大器耦合到位线和互补位线。 控制信号将参考电压耦合到互补位线。 在读出放大器使能之前，将正预充电电压施加到位线和互补位线。 存储单元响应于字线向位线输出电压，并且感测放大器响应于感测使能信号来感测位线和互补位线之间的差分电压。 公开了用于产生参考电压的电压调节器，优选地为正电源电压的约80％。 公开了一种感测由存储器单元存储的数据的方法。

    Controlling Global Bit Line Pre-Charge Time for High Speed eDRAM
    26.
    发明申请
    Controlling Global Bit Line Pre-Charge Time for High Speed eDRAM 有权
    控制高速eDRAM的全局位线预充电时间

    公开(公告)号：US20090141570A1

    公开(公告)日：2009-06-04

    申请号：US11970188

    申请日：2008-01-07

    申请人： Kuoyuan (Peter) Hsu ,  Bing Wang ,  Young Suk Kim

    发明人： Kuoyuan (Peter) Hsu ,  Bing Wang ,  Young Suk Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12 ,  G11C7/1048

    摘要： A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the memory cell, wherein the steps of starting the first GBL pre-charge and enabling the word line have a first time interval. The read operation includes starting a second GBL pre-charge on the GBL; and after the second GBL pre-charge is started, enabling the word line to read from the memory cell, wherein the steps of starting the second GBL pre-charge and enabling the word line have a second time interval. The first time interval is greater than the second time interval.

    摘要翻译： 操作存储器的方法包括对存储器单元执行写入操作和读取操作。 写入操作包括在GBL上启动第一个全局位线（GBL）预充电; 并且在开始第一GBL预充电之后，使得字线能够写入存储单元，其中启动第一GBL预充电和启用字线的步骤具有第一时间间隔。 读取操作包括在GBL上启动第二个GBL预充电; 并且在开始第二GBL预充电之后，使得字线能够从存储器单元读取，其中启动第二GBL预充电和使字线的步骤具有第二时间间隔。 第一时间间隔大于第二时间间隔。

    Tracking scheme for memory
    30.
    发明授权
    Tracking scheme for memory 有权
    内存跟踪方案

    公开(公告)号：US08976614B2

    公开(公告)日：2015-03-10

    申请号：US13026021

    申请日：2011-02-11

    申请人： Yong Zhang ,  Derek C. Tao ,  Dongsik Jeong ,  Young Suk Kim ,  Kuoyuan (Peter) Hsu

    发明人： Yong Zhang ,  Derek C. Tao ,  Dongsik Jeong ,  Young Suk Kim ,  Kuoyuan (Peter) Hsu

    IPC分类号： G11C7/06 ,  G11C7/22 ,  G11C11/419

    CPC分类号： G11C7/227 ,  G11C11/419

    摘要： A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row.

    摘要翻译： 存储器具有用于读取跟踪操作的跟踪电路。 存储器包括存储位单元阵列，跟踪列，跟踪行，耦合到存储器位单元阵列和跟踪行的读出放大器行以及读出放大器使能逻辑。 存储器还包括耦合到跟踪列和读出放大器使能逻辑的跟踪位线，以及耦合到跟踪行和读出放大器使能逻辑的跟踪字线。 跟踪电路被配置为沿着跟踪行在行时间延迟之前跟踪沿着跟踪列的列时间延迟。