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公开(公告)号：US07733724B2
公开(公告)日：2010-06-08
申请号：US11970188
申请日：2008-01-07
申请人： Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
发明人： Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/1048
摘要： A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the memory cell, wherein the steps of starting the first GBL pre-charge and enabling the word line have a first time interval. The read operation includes starting a second GBL pre-charge on the GBL; and after the second GBL pre-charge is started, enabling the word line to read from the memory cell, wherein the steps of starting the second GBL pre-charge and enabling the word line have a second time interval. The first time interval is greater than the second time interval.
摘要翻译： 操作存储器的方法包括对存储器单元执行写入操作和读取操作。 写入操作包括在GBL上启动第一个全局位线（GBL）预充电; 并且在开始第一GBL预充电之后，使得字线能够写入存储单元，其中启动第一GBL预充电和启用字线的步骤具有第一时间间隔。 读取操作包括在GBL上启动第二个GBL预充电; 并且在开始第二GBL预充电之后，使得字线能够从存储器单元读取，其中启动第二GBL预充电和使字线的步骤具有第二时间间隔。 第一时间间隔大于第二时间间隔。
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公开(公告)号：US08780652B2
公开(公告)日：2014-07-15
申请号：US13418968
申请日：2012-03-13
申请人： Bing Wang , Kuoyuan (Peter) Hsu , Young Suk Kim
发明人： Bing Wang , Kuoyuan (Peter) Hsu , Young Suk Kim
CPC分类号： G11C7/22 , G11C7/12 , G11C7/222 , G11C8/08 , G11C11/419 , G11C2207/005 , G11C2207/2254
摘要： In a method, a first edge of a first tracking signal in a first direction of a memory array is generated. A first edge of a second tracking signal in a second direction of the memory array is generated. A first edge of a write-timing control signal is generated based on a slower edge of the first edge the first tracking signal and of the first edge of the second tracking signal. The first edge of the write-timing control signal is used to generate a second edge of the second tracking signal.
摘要翻译： 在一种方法中，产生在存储器阵列的第一方向上的第一跟踪信号的第一边缘。 生成存储器阵列的第二方向上的第二跟踪信号的第一边缘。 基于第一边缘的较慢边缘和第二跟踪信号的第一边缘产生写时序控制信号的第一边沿。 写定时控制信号的第一边用于产生第二跟踪信号的第二边。
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公开(公告)号：US20090141570A1
公开(公告)日：2009-06-04
申请号：US11970188
申请日：2008-01-07
申请人： Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
发明人： Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/1048
摘要： A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the memory cell, wherein the steps of starting the first GBL pre-charge and enabling the word line have a first time interval. The read operation includes starting a second GBL pre-charge on the GBL; and after the second GBL pre-charge is started, enabling the word line to read from the memory cell, wherein the steps of starting the second GBL pre-charge and enabling the word line have a second time interval. The first time interval is greater than the second time interval.
摘要翻译： 操作存储器的方法包括对存储器单元执行写入操作和读取操作。 写入操作包括在GBL上启动第一个全局位线（GBL）预充电; 并且在开始第一GBL预充电之后，使得字线能够写入存储单元，其中启动第一GBL预充电和启用字线的步骤具有第一时间间隔。 读取操作包括在GBL上启动第二个GBL预充电; 并且在开始第二GBL预充电之后，使得字线能够从存储器单元读取，其中启动第二GBL预充电和使字线的步骤具有第二时间间隔。 第一时间间隔大于第二时间间隔。
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公开(公告)号：US08305827B2
公开(公告)日：2012-11-06
申请号：US12835197
申请日：2010-07-13
申请人： Derek C. Tao , Kuoyuan (Peter) Hsu , Dong Sik Jeong , Young Suk Kim , Young Seog Kim , Yukit Tang
发明人： Derek C. Tao , Kuoyuan (Peter) Hsu , Dong Sik Jeong , Young Suk Kim , Young Seog Kim , Yukit Tang
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, and a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes are electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.
摘要翻译： 存储器阵列包括以多行和多列布置的多个存储单元。 多列的列包括被配置为提供第一电压的第一电源节点，被配置为提供第二电压的第二电源节点和电耦合在一起并被配置为接收第一电压的多个内部供电节点， 该列中的多个存储单元的第二电压和多个内部接地节点。 内部接地节点电耦合在一起并且被配置为为列中的多个存储器单元提供至少两个电流路径。
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公开(公告)号：US08976614B2
公开(公告)日：2015-03-10
申请号：US13026021
申请日：2011-02-11
申请人： Yong Zhang , Derek C. Tao , Dongsik Jeong , Young Suk Kim , Kuoyuan (Peter) Hsu
发明人： Yong Zhang , Derek C. Tao , Dongsik Jeong , Young Suk Kim , Kuoyuan (Peter) Hsu
IPC分类号： G11C7/06 , G11C7/22 , G11C11/419
CPC分类号： G11C7/227 , G11C11/419
摘要： A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row.
摘要翻译： 存储器具有用于读取跟踪操作的跟踪电路。 存储器包括存储位单元阵列，跟踪列，跟踪行，耦合到存储器位单元阵列和跟踪行的读出放大器行以及读出放大器使能逻辑。 存储器还包括耦合到跟踪列和读出放大器使能逻辑的跟踪位线，以及耦合到跟踪行和读出放大器使能逻辑的跟踪字线。 跟踪电路被配置为沿着跟踪行在行时间延迟之前跟踪沿着跟踪列的列时间延迟。
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公开(公告)号：US08587991B2
公开(公告)日：2013-11-19
申请号：US13429082
申请日：2012-03-23
CPC分类号： G11C11/412
摘要： A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.
摘要翻译： 电路包括第一节点; 第二个节点; 具有耦合到第一节点的源极的第一PMOS晶体管，耦合到第一控制晶体管的漏极和由第一电压驱动的栅极; 以及第一NMOS晶体管，其具有耦合到第二节点的源极，耦合到第一控制晶体管的漏极和由第二电压驱动的栅极。 第一PMOS晶体管被配置为基于第一节点处的第一电压和第一节点电压自动关闭。 第一NMOS晶体管被配置为基于第二节点处的第二电压和第二节点电压自动关闭。 当第一PMOS晶体管，控制晶体管和第一NMOS晶体管导通时，第一节点电压降低，而第二电压升高。
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公开(公告)号：US08159862B2
公开(公告)日：2012-04-17
申请号：US12843366
申请日：2010-07-26
CPC分类号： G11C11/412
摘要： A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.
摘要翻译： 电路包括第一节点; 第二个节点; 具有耦合到第一节点的源极的第一PMOS晶体管，耦合到第一控制晶体管的漏极和由第一电压驱动的栅极; 以及第一NMOS晶体管，其具有耦合到第二节点的源极，耦合到第一控制晶体管的漏极和由第二电压驱动的栅极。 第一PMOS晶体管被配置为基于第一节点处的第一电压和第一节点电压自动关闭。 第一NMOS晶体管被配置为基于第二节点处的第二电压和第二节点电压自动关闭。 当第一PMOS晶体管，控制晶体管和第一NMOS晶体管导通时，第一节点电压降低，而第二电压升高。
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公开(公告)号：US09001613B2
公开(公告)日：2015-04-07
申请号：US13397415
申请日：2012-02-15
申请人： Bing Wang , Kuoyuan (Peter) Hsu
发明人： Bing Wang , Kuoyuan (Peter) Hsu
IPC分类号： G11C8/18 , G11C7/18 , G11C7/22 , G11C11/419
CPC分类号： G11C7/18 , G11C7/227 , G11C11/419
摘要： A tracking circuit in a memory macro includes a data line, a first tracking cell, and a plurality of transistors. The first tracking cell is electrically coupled to the data line. The plurality of transistors is electrically coupled to the data line. The plurality of transistors is configured to cause a delay on a transition of a signal of the data line based on a delay current. The signal of the data line is configured for use in generating a signal of a control line of a memory cell of the memory macro.
摘要翻译： 存储器宏中的跟踪电路包括数据线，第一跟踪单元和多个晶体管。 第一跟踪单元电耦合到数据线。 多个晶体管电耦合到数据线。 多个晶体管被配置为基于延迟电流在数据线的信号的转变上引起延迟。 数据线的信号被配置为用于产生存储器宏的存储单元的控制线的信号。
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公开(公告)号：US08964492B2
公开(公告)日：2015-02-24
申请号：US13560461
申请日：2012-07-27
申请人： Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
发明人： Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
CPC分类号： G11C7/222 , G11C7/12 , G11C7/227 , G11C11/419
摘要： A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell.
摘要翻译： 电路包括跟踪写入电路和写入电路。 基于跟踪写入电路的跟踪信号产生写入电路的各种写入信号。 写信号用于存储单元的写入操作。
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公开(公告)号：US08947949B2
公开(公告)日：2015-02-03
申请号：US13099809
申请日：2011-05-03
申请人： Bing Wang , Kuoyuan (Peter) Hsu
发明人： Bing Wang , Kuoyuan (Peter) Hsu
IPC分类号： G11C7/00 , G11C11/417
CPC分类号： G11C11/417 , G11C2207/2227
摘要： A circuit includes a memory cell having a ground reference node, a switch coupled to the ground reference node, and a mode changing circuit having an output coupled to the switch. The mode changing circuit is configured to change a logic state of the output between a first output logic state and a second output logic state in response to a change in an operational voltage and/or temperature, thereby set the memory cell in a first mode in which the ground reference node is at first reference level or in a second mode in which the ground reference node is at a second reference level different from the first reference level.
摘要翻译： 电路包括具有接地参考节点的存储器单元，耦合到接地参考节点的开关，以及具有耦合到开关的输出的模式改变电路。 模式改变电路被配置为响应于操作电压和/或温度的变化而改变第一输出逻辑状态和第二输出逻辑状态之间的输出的逻辑状态，从而将存储器单元设置为第一模式 其中地面参考节点处于第一参考水平或第二模式，其中地面参考节点处于与第一参考水平不同的第二参考水平。
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