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    PHARMACEUTICAL COMPOSITION CONTAINING AN ENDOCYTIC MOTIF AND PROTEIN TRANSDUCTION DOMAINS FOR PREVENTING OR TREATING CANCER
    22.
    发明申请
    PHARMACEUTICAL COMPOSITION CONTAINING AN ENDOCYTIC MOTIF AND PROTEIN TRANSDUCTION DOMAINS FOR PREVENTING OR TREATING CANCER 有权
    含有内源性MOTIF的蛋白质组合物和用于预防或治疗癌症的蛋白质转染域

    公开(公告)号：US20140066375A1

    公开(公告)日：2014-03-06

    申请号：US14002600

    申请日：2012-03-02

    申请人： Young Woo Park ,  Ki Won Jo ,  Kyu Won Cho ,  Ji Hyun Park ,  Soon Sil Hyun ,  Yun Jung Park

    发明人： Young Woo Park ,  Ki Won Jo ,  Kyu Won Cho ,  Ji Hyun Park ,  Soon Sil Hyun ,  Yun Jung Park

    IPC分类号： C07K7/08 ,  C07K14/00

    CPC分类号： C07K7/08 ,  A61K38/00 ,  C07K14/00 ,  C07K14/4753 ,  C07K2319/10

    摘要： The present invention relates to a novel endocytic motif, and in particular, to a fusion polypeptide including the motif represented by an amino acid sequence of SEQ ID NO. 1 and a protein transduction domain, a pharmaceutical composition for preventing or treating cancer including the same, and a method for treating cancer including the step of administering the composition. The present invention shows the effects of suppressing metastasis, infiltration, angiogenesis, and growth of cancer by specifically inhibiting c-Met endocytosis and effectively inhibiting HGF/c-Met signaling pathway associated with metastasis and growth of various types of cancer cells. Therefore, the present invention can be applied to an anticancer agent for various types of cancer.

    摘要翻译： 本发明涉及一种新的内吞基序，特别涉及包含由SEQ ID NO：1的氨基酸序列表示的基序的融合多肽。 1和蛋白质转导结构域，用于预防或治疗包括其的癌症的药物组合物，以及治疗癌症的方法，包括施用组合物的步骤。 本发明通过特异性抑制c-Met内吞作用并有效抑制与各种癌细胞的转移和生长相关的HGF / c-Met信号通路，显示抑制癌转移，浸润，血管生成和生长的作用。 因此，本发明可以应用于各种癌症的抗癌剂。

    Non-Volatile Memory Devices and Manufacturing Methods Thereof
    24.
    发明申请
    Non-Volatile Memory Devices and Manufacturing Methods Thereof 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20150132915A1

    公开(公告)日：2015-05-14

    申请号：US14457220

    申请日：2014-08-12

    申请人： Jin Taek Park ,  Young Woo Park ,  Jae Duk Lee

    发明人： Jin Taek Park ,  Young Woo Park ,  Jae Duk Lee

    IPC分类号： H01L29/66 ,  H01L27/115

    CPC分类号： H01L29/513 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7789 ,  H01L29/7926

    摘要： There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer

    摘要翻译： 提供了一种制造非易失性存储器件的方法，包括：在衬底的顶表面上交替堆叠多个绝缘层和多个导电层; 形成露出所述基板的顶表面和所述绝缘层和所述导电层的侧表面的开口; 在所述导电层的至少暴露的侧表面上形成抗氧化层; 在所述抗氧化层上形成栅介电层，所述栅极介电层包括依次形成在所述抗氧化层上的阻挡层，电荷存储层和隧穿层; 以及在隧道层上形成沟道区

    Non-volatile memory devices and manufacturing methods thereof
    25.
    发明授权
    Non-volatile memory devices and manufacturing methods thereof 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US09564519B2

    公开(公告)日：2017-02-07

    申请号：US14457220

    申请日：2014-08-12

    申请人： Jin Taek Park ,  Young Woo Park ,  Jae Duk Lee

    发明人： Jin Taek Park ,  Young Woo Park ,  Jae Duk Lee

    IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/792 ,  H01L27/115 ,  G11C16/04

    CPC分类号： H01L29/513 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7789 ,  H01L29/7926

    摘要： There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.

    摘要翻译： 提供了一种制造非易失性存储器件的方法，包括：在衬底的顶表面上交替堆叠多个绝缘层和多个导电层; 形成露出所述基板的顶表面和所述绝缘层和所述导电层的侧表面的开口; 在所述导电层的至少暴露的侧表面上形成抗氧化层; 在所述抗氧化层上形成栅介电层，所述栅极介电层包括依次形成在所述抗氧化层上的阻挡层，电荷存储层和隧穿层; 以及在隧道层上形成沟道区。

    Method of forming storage nodes in a DRAM
    26.
    发明授权
    Method of forming storage nodes in a DRAM 有权
    在DRAM中形成存储节点的方法

    公开(公告)号：US06482696B2

    公开(公告)日：2002-11-19

    申请号：US09901048

    申请日：2001-07-10

    申请人： Young Woo Park

    发明人： Young Woo Park

    IPC分类号： H01L218242

    CPC分类号： H01L28/91 ,  H01L21/31625 ,  H01L27/10852

    摘要： A method of forming capacitor over bit line storage nodes in dynamic random access memory cell includes forming a multi-layered structure having at least two silicon oxide layers as a thick molding layer, e.g., to a thickness of more than 8000 Å. The at least two silicon oxide layers are disposed to have an etch speed of relatively lower-positioned silicon oxide layer to be relatively faster than that of relatively upper-positioned silicon oxide layer. Holes are then etched in the multi-layered structure, thereby reducing a width differential between the upper and lower layers.

    摘要翻译： 在动态随机存取存储器单元中的位线存储节点上形成电容器的方法包括形成具有至少两个氧化硅层的多层结构作为厚的成型层，例如厚度超过8000埃。 至少两个氧化硅层被设置为具有相对较低位置的氧化硅层的蚀刻速度将比相对较高位置的氧化硅层的蚀刻速度相对更快。 然后在多层结构中蚀刻孔，从而减小上层和下层之间的宽度差。

    Three dimensional semiconductor memory devices and methods of fabricating the same
    29.
    发明授权
    Three dimensional semiconductor memory devices and methods of fabricating the same 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US08952443B2

    公开(公告)日：2015-02-10

    申请号：US13222173

    申请日：2011-08-31

    申请人： Sung-Il Chang ,  Young Woo Park ,  Jae Goo Lee

    发明人： Sung-Il Chang ,  Young Woo Park ,  Jae Goo Lee

    IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L21/28

    CPC分类号： H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/42324 ,  H01L29/4234

    摘要： A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.

    摘要翻译： 一种3D半导体器件包括：电极结构，其具有堆叠在基板上的电极，穿透电极结构的半导体图案，插入在半导体图案和电极结构之间的电荷存储图案，以及插入在电荷存储图案和电极结构之间的绝缘图案。 每个隔离绝缘图案包围半导体图案，并且电荷存储图案彼此水平间隔并且以这样的方式配置，以使得每个隔离绝缘图案围绕相应的一个半导体图案设置。 而且，每个电荷存储图案包括多个水平段，每个水平段插入垂直相邻的电极之间。