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85 条记录 (耗时 0.023 秒)

    Integrated circuit package having inductance loop formed from a bridge interconnect
    21.
    发明授权
    Integrated circuit package having inductance loop formed from a bridge interconnect 有权
    集成电路封装，其具有由桥互连形成的电感环路

    公开(公告)号：US07071535B2

    公开(公告)日：2006-07-04

    申请号：US10927152

    申请日：2004-08-27

    申请人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonban Park ,  Kyeongho Lee

    发明人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonban Park ,  Kyeongho Lee

    IPC分类号： H01L29/00 ,  H03B7/14

    CPC分类号： H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1265 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.

    摘要翻译： 集成电路封装包括由引线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。 在一个实施例中，电感回路由将集成电路芯片上的第一接合焊盘连接到封装的第一I / O引脚的第一引线和将芯片上的第二接合焊盘连接到第二引线的第二引线形成 封装的I / O引脚。 为了完成电感环路，第一和第二I / O引脚通过引脚之间的导电桥连接。 可以通过使I / O引脚具有单一结构来形成桥。 在另一个实施例中，桥由位于封装衬底的表面上或在该衬底内的金属化层形成。 I / O引脚优选为彼此相邻的引脚; 然而，环路可以基于例如环路长度要求，空间考虑和/或其他设计或功能因素的I / O引脚的不相邻连接形成。 通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。 此外，集成电路可以在各种系统中的任何一个中实现，其中的至少一个参数由封装的电感器环的长度来控制。

    Low noise amplifier having improved linearity
    22.
    发明申请
    Low noise amplifier having improved linearity 有权
    低噪声放大器具有改善的线性度

    公开(公告)号：US20080252377A1

    公开(公告)日：2008-10-16

    申请号：US11976911

    申请日：2007-10-29

    申请人： Seung-Wook Lee ,  Deok Hee Lee ,  Eunseok Song ,  Joonbae Park ,  Kyeongho Lee

    发明人： Seung-Wook Lee ,  Deok Hee Lee ,  Eunseok Song ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H03G3/30 ,  H04B1/16

    CPC分类号： H03F1/223 ,  H03F3/193 ,  H03F2200/372

    摘要： Embodiments of the present general inventive concept include a low noise amplifier and method with an improved linearity while reducing a noise disadvantage (e.g., increase). One embodiment of a low noise amplifier can include a first transistor to receive an input signal at a control terminal thereof, a second transistor having a first terminal coupled to a second terminal of the first transistor, an envelope detector to output a control signal corresponding to a characteristic of the input signal and an envelope amplifier to amplify the control signal to be applied to a control terminal of the second transistor.

    摘要翻译： 本发明总体构思的实施例包括具有改善的线性度的低噪声放大器和方法，同时降低噪声不利（例如增加）。 低噪声放大器的一个实施例可以包括在其控制端接收输入信号的第一晶体管，具有耦合到第一晶体管的第二端的第一端的第二晶体管，用于输出对应于 输入信号的特性和包络放大器，放大要施加到第二晶体管的控制端的控制信号。

    Low noise amplifier having improved linearity
    23.
    发明授权
    Low noise amplifier having improved linearity 有权
    低噪声放大器具有改善的线性度

    公开(公告)号：US07812672B2

    公开(公告)日：2010-10-12

    申请号：US11976911

    申请日：2007-10-29

    申请人： Seung-Wook Lee ,  Deok Hee Lee ,  Eunseok Song ,  Joonbae Park ,  Kyeongho Lee

    发明人： Seung-Wook Lee ,  Deok Hee Lee ,  Eunseok Song ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H03F3/30

    CPC分类号： H03F1/223 ,  H03F3/193 ,  H03F2200/372

    摘要： Embodiments of the present general inventive concept include a low noise amplifier and method with an improved linearity while reducing a noise disadvantage (e.g., increase). One embodiment of a low noise amplifier can include a first transistor to receive an input signal at a control terminal thereof, a second transistor having a first terminal coupled to a second terminal of the first transistor, an envelope detector to output a control signal corresponding to a characteristic of the input signal and an envelope amplifier to amplify the control signal to be applied to a control terminal of the second transistor.

    摘要翻译： 本发明总体构思的实施例包括具有改善的线性度的低噪声放大器和方法，同时降低噪声不利（例如增加）。 低噪声放大器的一个实施例可以包括在其控制端接收输入信号的第一晶体管，具有耦合到第一晶体管的第二端的第一端的第二晶体管，用于输出对应于 输入信号的特性和包络放大器，放大要施加到第二晶体管的控制端的控制信号。

    Apparatus for measuring in-phase and quadrature (IQ) imbalance
    25.
    发明授权
    Apparatus for measuring in-phase and quadrature (IQ) imbalance 有权
    用于测量同相和正交（IQ）不平衡的装置

    公开(公告)号：US07995645B2

    公开(公告)日：2011-08-09

    申请号：US12027762

    申请日：2008-02-07

    申请人： Kyeongho Lee ,  Joonbae Park ,  Jeong Woo Lee ,  Seung-Wook Lee ,  Eal Wan Lee

    发明人： Kyeongho Lee ,  Joonbae Park ,  Jeong Woo Lee ,  Seung-Wook Lee ,  Eal Wan Lee

    IPC分类号： H04B3/46

    CPC分类号： H03D7/166 ,  H03D3/009 ,  H04L25/061 ,  H04L27/364 ,  H04L27/3863 ,  H04L2027/0016

    摘要： The present general inventive concept relates to apparatuses and/or methods for measuring an in-phase and quadrature (IQ) imbalance. In one embodiment, a signal generator can provide a first IQ signal of a DC component during a first period and the first IQ signal of a first angular frequency during a second period, an IQ up-conversion mixer can up-convert the first IQ signal by a second angular frequency during the first period and up-convert the first IQ signal by a third angular frequency during the second period to output a second IQ signal, an IQ down-conversion mixer can down-convert the second IQ signal by the third angular frequency to output a third IQ signal and an IQ imbalance detector can obtain a first IQ imbalance (e.g., Rx IQ imbalance) from the third IQ signal during the first period and a second IQ imbalance (e.g., Tx/Rx IQ imbalance) during the second period.

    摘要翻译： 本总体发明构思涉及用于测量同相和正交（IQ）不平衡的装置和/或方法。 在一个实施例中，信号发生器可以在第一周期期间提供DC分量的第一IQ信号，并且在第二周期期间提供第一角频率的第一IQ信号，IQ上变频混频器可以上变频第一IQ信号 在第一周期期间以第二角度频率进行第二角度频率，并且在第二周期期间将第一IQ信号上升转换第三角度频率以输出第二IQ信号，IQ降频转换混频器可以将第二IQ信号下变频第三IQ信号 输出第三IQ信号和IQ不平衡检测器的角频率可以在第一周期期间从第三IQ信号和第二IQ不平衡（例如，Tx / Rx IQ不平衡）获得第一IQ不平衡（例如，Rx IQ不平衡） 第二期。

    System and method for filtering signals in a transceiver
    28.
    发明申请
    System and method for filtering signals in a transceiver 有权
    用于对收发器中的信号进行滤波的系统和方法

    公开(公告)号：US20050048928A1

    公开(公告)日：2005-03-03

    申请号：US10927013

    申请日：2004-08-27

    申请人： Young-Deuk Jeon ,  Seung-Wook Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    发明人： Young-Deuk Jeon ,  Seung-Wook Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H04B1/38

    CPC分类号： H04B1/1027 ,  H03H11/1252 ,  H03H11/1291 ,  H03J1/0008 ,  H04B1/44

    摘要： A system and method for filtering signals in a communications system reduces hardware and chip size requirements by selectively connecting a filter along transmitter and receiver paths of a transceiver. In operation, a controller generated signals for connecting the filter along the transmitter path when the transceiver is in transmitter mode and for connecting the filter along the receiver path when the transmitter is in receiver mode. The controller then generates additional signals for setting one or more parameters of the filter based on the path connected, or put differently based on the operational mode of the transceiver. In a variation, the controller sets the parameters of additional elements coupled to the filter as a way of further controlling processing of the transmitter and receiver signals. The system and method are particularly well suited to controlling the filtering of signals at the front-end of the transceiver having a direct-conversion architecture and in general ones performing time-multiplexing applications.

    摘要翻译： 用于对通信系统中的信号进行滤波的系统和方法通过沿收发器的发射机和接收机路径选择性地连接滤波器来降低硬件和芯片尺寸的要求。 在操作中，当收发器处于发射机模式时，控制器产生用于沿着发射机路径连接滤波器的信号，并且当发射机处于接收机模式时，控制器沿着接收机路径连接滤波器。 然后，控制器产生附加信号，用于基于连接的路径设置滤波器的一个或多个参数，或者基于收发器的操作模式进行不同的设置。 在一个变型中，控制器设置耦合到滤波器的附加元件的参数作为进一步控制发射机和接收机信号的处理的一种方式。 该系统和方法特别适用于控制在具有直接转换架构的收发器的前端处的信号的滤波，并且通常执行时间复用应用。