公开(公告)号：US06873550B2

公开(公告)日：2005-03-29

申请号：US10636173

申请日：2003-08-07

申请人： Andrei Mihnea

发明人： Andrei Mihnea

IPC分类号： G11C16/04 ,  G11C16/10

CPC分类号： G11C16/0475 ,  G11C16/0466 ,  G11C16/10

摘要： A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled to the gale input. A constant positive current is input to one of the source/drain regions. The remaining source/drain region is either allowed to float, is coupled to a ground potential, or is coupled to the first source/drain region.

摘要翻译： 氮化物只读存储器（NROM）单元可以通过向栅极输入施加斜坡电压，对两个源极/漏极区中的一个施加恒定电压，并将剩余的源极/漏极区的接地电位编程。 为了擦除NROM单元，将恒定电压耦合到大风输入端。 恒定的正电流被输入到源/漏区之一。 剩余的源极/漏极区域被允许浮动，耦合到接地电位，或耦合到第一源极/漏极区域。

公开(公告)号：US06587376B2

公开(公告)日：2003-07-01

申请号：US10238317

申请日：2002-09-10

申请人： Andrei Mihnea ,  Paul J. Rudeck ,  Chun Chen

发明人： Andrei Mihnea ,  Paul J. Rudeck ,  Chun Chen

IPC分类号： G11C1604

CPC分类号： G11C16/12

摘要： A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

公开(公告)号：US06493280B2

公开(公告)日：2002-12-10

申请号：US09982682

申请日：2001-10-22

申请人： Andrei Mihnea ,  Jeffrey Kessenich ,  Chun Chen

发明人： Andrei Mihnea ,  Jeffrey Kessenich ,  Chun Chen

IPC分类号： G11C700

CPC分类号： G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445

摘要： A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.

公开(公告)号：US06445619B1

公开(公告)日：2002-09-03

申请号：US09920364

申请日：2001-08-01

申请人： Andrei Mihnea ,  Paul J. Rudeck ,  Chun Chen

发明人： Andrei Mihnea ,  Paul J. Rudeck ,  Chun Chen

IPC分类号： G11C1604

CPC分类号： G11C16/12

摘要： A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

摘要翻译： 闪存单元包括栅极，漏极，源极，浮动栅极和控制栅极。 通过向栅极施加第一电压，向漏极施加第二电压，并且通过向漏极施加第三电压，通过在深耗尽区域上诱导约四伏和六伏之间的电压降来对闪存单元进行编程 资源。 在编程操作期间，通道电流大约为零，并且第一电压以与注入电流成比例的速率斜坡化。

公开(公告)号：US06434045B1

公开(公告)日：2002-08-13

申请号：US09876674

申请日：2001-06-07

申请人： Andrei Mihnea ,  Paul J. Rudeck ,  Chun Chen

发明人： Andrei Mihnea ,  Paul J. Rudeck ,  Chun Chen

IPC分类号： G11C1604

摘要： A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

公开(公告)号：US08557654B2

公开(公告)日：2013-10-15

申请号：US12966735

申请日：2010-12-13

申请人： Peter Rabkin ,  Andrei Mihnea

发明人： Peter Rabkin ,  Andrei Mihnea

IPC分类号： H01L21/329 ,  H01L21/33 ,  H01L27/02 ,  H01L23/60 ,  H01L23/62

CPC分类号： H01L27/0255 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/2409 ,  H01L27/2481 ,  H01L29/6609 ,  H01L29/66121 ,  H01L29/861 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

摘要： A punch-through diode and method of fabricating the same are disclosed herein. The punch-through diode may be used as a steering element in a memory device having a reversible resistivity-switching element. For example, a memory cell may include a reversible resistivity-switching element in series with a punch-through diode. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. In other words, the ratio of Ion/Ioff is high. Therefore, the punch-through diode is compatible with bipolar switching in cross-point memory arrays having resistive switching elements.

摘要翻译： 本文公开了穿通二极管及其制造方法。 穿通二极管可以用作具有可逆电阻率开关元件的存储器件中的转向元件。 例如，存储单元可以包括与穿通二极管串联的可逆电阻率开关元件。 穿通二极管允许交叉点存储器阵列的双极性操作。 穿通二极管可具有对称的非线性电流/电压关系。 穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。 换句话说，Ion / Ioff的比例很高。 因此，穿通二极管与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。

公开(公告)号：US08351243B2

公开(公告)日：2013-01-08

申请号：US12947553

申请日：2010-11-16

申请人： Andrei Mihnea ,  George Samachisa

发明人： Andrei Mihnea ,  George Samachisa

IPC分类号： G11C11/00 ,  H01L29/06

CPC分类号： G11C13/003 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/79 ,  H01L27/2454 ,  H01L27/2463

摘要： A nonvolatile memory device with a first conductor extending in a first direction and a semiconductor element above the first conductor. The semiconductor element includes a source, a drain and a channel of a field effect transistor (JFET or MOSFET). The nonvolatile memory device also includes a second conductor above the semiconductor element, the second conductor extending in a second direction. The nonvolatile memory device also includes a resistivity switching material disposed between the first conductor and the semiconductor element or between the second conductor and the semiconductor element. The JFET or MOSFET includes a gate adjacent to the channel, and the MOSFET gate being self-aligned with the first conductor.

摘要翻译： 一种非易失性存储器件，具有沿第一方向延伸的第一导体和位于第一导体上方的半导体元件。 半导体元件包括场效应晶体管（JFET或MOSFET）的源极，漏极和沟道。 非易失性存储器件还包括在半导体元件上方的第二导体，第二导​​体沿第二方向延伸。 非易失性存储器件还包括设置在第一导体和半导体元件之间或第二导体与半导体元件之间的电阻率切换材料。 JFET或MOSFET包括与沟道相邻的栅极，并且MOSFET栅极与第一导体自对准。

公开(公告)号：US20120302029A1

公开(公告)日：2012-11-29

申请号：US13571100

申请日：2012-08-09

申请人： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

发明人： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

IPC分类号： H01L21/02

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/24

摘要： A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.

摘要翻译： 描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。 穿通二极管允许交叉点存储器阵列的双极性操作。 穿通二极管可具有对称的非线性电流/电压关系。 穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。 因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。 穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

公开(公告)号：US20120120709A1

公开(公告)日：2012-05-17

申请号：US12947553

申请日：2010-11-16

申请人： Andrei Mihnea ,  George Samachisa

发明人： Andrei Mihnea ,  George Samachisa

IPC分类号： G11C11/56 ,  H01L21/8239 ,  H01L45/00

CPC分类号： G11C13/003 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/79 ,  H01L27/2454 ,  H01L27/2463

摘要： A nonvolatile memory device with a first conductor extending in a first direction and a semiconductor element above the first conductor. The semiconductor element includes a source, a drain and a channel of a field effect transistor (JFET or MOSFET). The nonvolatile memory device also includes a second conductor above the semiconductor element, the second conductor extending in a second direction. The nonvolatile memory device also includes a resistivity switching material disposed between the first conductor and the semiconductor element or between the second conductor and the semiconductor element. The JFET or MOSFET includes a gate adjacent to the channel, and the MOSFET gate being self-aligned with the first conductor.

摘要翻译： 一种非易失性存储器件，具有沿第一方向延伸的第一导体和位于第一导体上方的半导体元件。 半导体元件包括场效应晶体管（JFET或MOSFET）的源极，漏极和沟道。 非易失性存储器件还包括在半导体元件上方的第二导体，第二导​​体沿第二方向延伸。 非易失性存储器件还包括设置在第一导体和半导体元件之间或第二导体与半导体元件之间的电阻率切换材料。 JFET或MOSFET包括与沟道相邻的栅极，并且MOSFET栅极与第一导体自对准。

公开(公告)号：US20110280076A1

公开(公告)日：2011-11-17

申请号：US12848458

申请日：2010-08-02

申请人： George Samachisa ,  Johann Alsmeier ,  Andrei Mihnea

发明人： George Samachisa ,  Johann Alsmeier ,  Andrei Mihnea

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L45/00 ,  H01L29/788

CPC分类号： H01L27/1214 ,  B82Y10/00 ,  G11C16/0483 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory device includes at least one junctionless transistor and a storage region. The junctionless transistor includes a junctionless, heavily doped semiconductor channel having two dimensions less than 100 nm.

摘要翻译： 非易失性存储器件包括至少一个无接头晶体管和存储区域。 无连接晶体管包括具有小于100nm的二维的无连接的重掺杂半导体沟道。