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公开(公告)号：US07125763B1
公开(公告)日：2006-10-24
申请号：US09885426
申请日：2001-06-19
IPC分类号： H01L21/8238
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： A process of fabricating a memory cell that includes a substrate that has a first region and a second region with a channel therebetween by forming a gate above the channel of the substrate, forming a bitline and siliciding the bitline.
摘要翻译： 一种制造存储单元的方法，该存储单元包括具有第一区域和第二区域的衬底，所述第一区域和第二区域之间具有通道，通过在衬底的沟道上形成栅极，形成位线并硅化位线。
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22.发明授权Method of controlling program threshold voltage distribution of a dual cell memory device 有权控制双电池存储器件的程序阈值电压分布的方法公开(公告)号：US06822909B1
公开(公告)日：2004-11-23
申请号：US10422090
申请日：2003-04-24
IPC分类号： G11C1134
CPC分类号： G11C16/0475 , G11C11/5671 , G11C16/3454
摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. The method can include applying an initial program pulse to the memory device; comparing the threshold voltage of the memory device with a verify threshold voltage; and if the threshold voltage of the memory device is less than the verify threshold voltage, applying a second program pulse to the memory device during which at least one condition of the second program pulse is modified from the initial program pulse.
摘要翻译： 一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。 该方法可以包括将初始编程脉冲施加到存储器件; 将存储器件的阈值电压与验证阈值电压进行比较; 并且如果所述存储器件的阈值电压小于所述验证阈值电压，则向所述存储器件施加第二编程脉冲，在所述存储器件期间，从所述初始编程脉冲修改所述第二编程脉冲的至少一个条件。
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公开(公告)号：US06744675B1
公开(公告)日：2004-06-01
申请号：US10305756
申请日：2002-11-26
申请人： Wei Zheng , Mark W. Randolph
发明人： Wei Zheng , Mark W. Randolph
IPC分类号： G11C1600
CPC分类号： G11C16/3413 , G11C16/0475 , G11C16/10 , G11C16/3404
摘要： In a non-volatile SONOS-type memory device having a charge storing layer disposed between top and bottom dielectric layers, a method of programming the memory device includes selectively storing charge in an upper portion of the charge storing layer. The method includes performing a channel hot electron injection procedure followed by a soft erase operation in which charge within a bottom portion of the first charging cell is removed. A verification procedure is performed to determine whether at least one charge storing cell is in a programmed state. The method provides a programmed cell in which the stored charge is disposed adjacent an upper portion of the cell near the top dielectric.
摘要翻译： 在具有设置在顶部和底部介电层之间的电荷存储层的非易失性SONOS型存储器件中，对存储器件进行编程的方法包括在电荷存储层的上部选择性地存储电荷。 该方法包括执行通道热电子注入程序，随后进行软擦除操作，其中去除第一充电单元的底部内的电荷。 执行验证过程以确定至少一个电荷存储单元是否处于编程状态。 该方法提供了一个编程单元，其中存储的电荷邻近靠近顶部电介质的单元的上部附近设置。
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24.发明授权Method for fabricating nitride memory cells using a floating gate fabrication process 有权使用浮栅制造工艺制造氮化物存储单元的方法公开(公告)号：US06743677B1
公开(公告)日：2004-06-01
申请号：US10306529
申请日：2002-11-27
IPC分类号： H01L21336
CPC分类号： H01L21/28282
摘要： The present invention is a method for fabricating nitride memory cells using a floating gate fabrication process. In one embodiment of the present invention, the fabrication process of a floating gate memory cell is accessed. The floating gate memory cell fabrication process is then altered to produce an altered floating gate memory cell fabrication process. The altered floating gate memory cell fabrication process is then used to form a nitride memory cell.
摘要翻译： 本发明是使用浮栅制造工艺制造氮化物存储单元的方法。 在本发明的一个实施例中，访问浮动栅极存储单元的制造过程。 然后改变浮动栅极存储器单元制造工艺以产生改变的浮动栅极存储器单元制造工艺。 然后使用改变的浮动栅极存储单元制造工艺来形成氮化物存储单元。
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25.发明授权Replacing layers of an intergate dielectric layer with high-K material for improved scalability 有权用高K材料代替隔间介电层的层，以提高可扩展性公开(公告)号：US06693321B1
公开(公告)日：2004-02-17
申请号：US10145952
申请日：2002-05-15
申请人： Wei Zheng , Arvind Halliyal , Mark W. Randolph
发明人： Wei Zheng , Arvind Halliyal , Mark W. Randolph
IPC分类号： H01L2976
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/511
摘要： A method of making and a semiconductor device formed on a semiconductor substrate having an active region. The semiconductor device includes a gate dielectric layer disposed on the semiconductor substrate. A floating gate is formed on the gate dielectric layer and defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. A control gate is formed above the floating gate. Further, the semiconductor device includes an intergate dielectric layer interposed between the floating gate and the control gate. The intergate dielectric layer including a first, a second and a third layers. The first layer formed on the floating gate. The second layer formed on the first layer. The third layer formed on the second layer. Each of the first, second and third layers has a dielectric constant greater than SiO2 and an electrical equivalent thickness of less than about 50 angstroms (Å) of SiO2.
摘要翻译： 一种制造方法和形成在具有活性区域的半导体衬底上的半导体器件。 半导体器件包括设置在半导体衬底上的栅介质层。 在栅极电介质层上形成浮置栅极，并且限定了介于形成在半导体衬底的有源区域内的源极和漏极之间的沟道。 控制栅极形成在浮动栅极上方。 此外，半导体器件包括介于浮置栅极和控制栅极之间的隔间介电层。 隔间介电层包括第一层，第二层和第三层。 在浮动门上形成的第一层。 形成在第一层上的第二层。 形成在第二层上的第三层。 第一层，第二层和第三层中的每一层具有大于SiO 2的介电常数和少于约50埃（SiO 2）的电当量厚度。
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公开(公告)号：US09196624B2
公开(公告)日：2015-11-24
申请号：US13545469
申请日：2012-07-10
IPC分类号： H01L21/336 , H01L27/115 , H01L21/28
CPC分类号： H01L27/11521 , H01L21/28273
摘要： Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region.
摘要翻译： 描述了制作字线保护结构的方法和系统。 如上所述，字线保护结构包括与存储器核心区域相邻形成的多晶硅结构。 多晶硅结构包括位于多晶硅结构的芯侧的第一掺杂区和位于多晶硅结构的脊侧的第二掺杂区。 位于第一和第二掺杂区域之间的未掺杂区域。 导电层形成在多晶硅结构的顶部，并且被布置成使得其在第一掺杂区域和未掺杂区域或第二掺杂区域和未掺杂区域之间的过渡处不接触未掺杂区域。
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27.发明授权公开(公告)号：US08957472B2
公开(公告)日：2015-02-17
申请号：US13357252
申请日：2012-01-24
IPC分类号： H01L29/792 , H01L27/115 , H01L29/66
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
摘要翻译： 提供了存储器件和制造方法。 存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。 栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。 存储器件包括一对位线，其中位线具有下部分和基本上梯形的上部部分。
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28.发明授权公开(公告)号：US08125018B2
公开(公告)日：2012-02-28
申请号：US11033588
申请日：2005-01-12
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
摘要翻译： 提供了存储器件和制造方法。 存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。 栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。 存储器件包括一对位线，其中位线具有下部分和基本上梯形的上部部分。
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公开(公告)号：US20090161466A1
公开(公告)日：2009-06-25
申请号：US11961772
申请日：2007-12-20
CPC分类号： G11C16/3418 , G11C16/10 , G11C16/3431
摘要： Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate.
摘要翻译： 本文公开了通过程序状态改写提供闪速存储器件的扩展数据保存。 作为示例，可以评估存储器单元或存储器单元组以确定单元的程序状态。 如果单元处于编程状态，与自然或非编程状态相反，则可以将充电电平，电压电平和/或类似物重写为与程序状态相关联的默认电平，而不擦除 电池第一。 因此，可以避免用于刷新需要重写和擦除的通常降低存储器单元的存储容量的小区程序状态的常规机制。 结果，存储在闪速存储器中的数据可以以减轻内存完整性损失的方式刷新，相对于可以以相对较高的速率降低存储器完整性的传统机制提供实质的益处。
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公开(公告)号：US07001807B1
公开(公告)日：2006-02-21
申请号：US10997345
申请日：2004-11-24
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L21/31
CPC分类号： H01L29/513 , H01L21/28282 , H01L29/512 , H01L29/517 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
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